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10 - bit, 4 oversampling sdtv video decoder data sheet adv7180 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 - 2012 analog devices, inc. all right s reserved. rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one techno logy way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 - 2012 analog devices, inc. all rights reserved. features qualified for a utomotive applications worldwide ntsc/pal/secam color demodulation support one 10 - bit adc, 4 oversampling for cvbs, 2 oversampling for y/c mode, and 2 oversampling for yprpb (per channel) 3 video input channels with on - chip antia liasing filter cvbs (composite), y/c (s -v ideo), and yprpb (component) video input support 5- line adaptive comb filters and cti/dnr video enhancement mini - tbc functionality provided by adaptive d igital line l ength t racking (adllt), signal processing, and e nhanced fifo manage ment integrated agc with adaptive peak white mode macrovision copy protection detection ntsc/pal/secam autodetection 8- bit itu - r bt.656 ycrcb 4:2:2 output and hs, vs, and field 1 1.0 v analog input signal range full - featured vbi data slicer with teletext support (wst) power - down mode and ultralow sleep mode current 2- wire serial mpu interface (i 2 c compatible) single 1.8 v supply possible 1.8 v analog, 1.8 v pll, 1.8 v digital, 1.8 v to 3.3 v i/o supply ?10c to +70c commercial temperature grade ?40c to +85c industrial /automotive qualified temperature grade ?40c to +125c temperature grade for automotive qualified 4 package types 64- lead, 10 mm 10 mm, rohs - compliant lqfp 48- lead, 7 mm 7 mm, rohs - compliant lqfp 40- lead, 6 mm 6 mm, rohs - compliant lfcsp 32- lead, 5 mm 5 mm, rohs - compliant lfcsp general description the adv7180 automatically detects and converts standard analog baseband television signals compatible with worldwide ntsc, pal, and secam standards into 4:2:2 component video data compatible with the 8 - bit itu - r bt.656 interface standard. the simple digital output interface connects gluelessly to a wide range of mpeg encoders, codecs, mobile video processors, and analog devices, inc., digital video encoders, such as the adv7391 . external hs, vs, and field signals provide timing references for lcd controllers and other video asics, if required. accurate 10- bit analog - to - digital conversion provides professional quality applications digita l camcorders and pdas low cost sdtv pip decoders for digital tvs multichannel dvrs for video security av receivers and video transcoding pci - /usb - based video capture and tv tuner cards personal media players and recorders smartphone/multimedia handsets in - car/automotive infotainment units rearview camera/vehicle safety systems functional block dia gram 05700-001 a in 1 a in 2 xtal1 xtal a in 3 a in 4 1 a in 5 1 a in 6 1 analog video inputs aa filter aa filter aa filter digital processing block 2d comb vbi slicer color demod sclk sdata alsb reset pwrdwn 4 1 only available on 64-lead package and 48-lead packages. 2 16-bit only available on 64-lead package. 3 48-lead, 40-lead, and 32-lead package uses one lead for vs/field. 4 not available on 32-lead package. 5 only available on 48-lead and 64-lead packages. 10-bit, 86mhz adc reference pll adllt processing clock processing block i 2 c/control mux block fifo output block adv7180 sha a/d vs llc hs sfl intrq p15 to p0 8-bit/16-bit 2 pixel data field 3 gpo 5 figure 1. video performance for consumer applications with true 8 - bit data resolution. three analog video input channels accept sta ndard composite, s - video, or component video signals, supporting a wide range of consumer video sources. agc and clamp - restore circuitry allow an input video signal peak - to - peak range to 1.0 v. alternatively, these can be bypassed for manual settings. the line - locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with 5% line length variation. output control signals allow glueless interface connections in many applicat ions. the adv7180 is programmed via a 2 - wire, serial bidirectional port (i 2 c? compatible) and is fabricated in a 1.8 v cmos process . its monolithic cmos construction ensures greater functionality with lower power dissipation. lfcsp package options make the decoder ideal for space - constrained portable applications. the 64 -l ead lqfp package is pin compatible with the adv7181c . 1 the 48 - lead lqfp , 40 - lead lfcsp , and 32 - lead lfcsp use one pin to output vs or field.
adv7180 data sheet rev. g | page 2 of 120 table of contents features .............................................................................................. 1 general description ......................................................................... 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 introduction ...................................................................................... 5 analog front end ......................................................................... 5 standard definition processor .................................................... 5 functional block diagrams ............................................................. 6 specificatio ns ..................................................................................... 8 electrical characteristics ............................................................. 8 video specifications ..................................................................... 9 timing specifications ................................................................ 10 analog specifications ................................................................. 11 thermal specifications .............................................................. 11 absolute maximum ratings .......................................................... 12 esd caution ................................................................................ 12 pin configurations and function descriptions ......................... 13 32- lead lfcsp ........................................................................... 13 40- lead lfcsp ........................................................................... 14 64- lead lqfp ............................................................................. 15 48- lead lqfp ............................................................................. 17 analog front end ........................................................................... 18 input configuration ................................................................... 19 power - on reset ...................................................................... 20 analog input muxing ................................................................ 20 antialiasing filters ..................................................................... 21 global control registers ............................................................... 22 power - saving modes .................................................................. 22 reset control .............................................................................. 22 global pin control ..................................................................... 22 global status register .................................................................... 24 identification ............................................................................... 24 status 1 ......................................................................................... 24 autodetection result .................................................................. 24 status 2 ......................................................................................... 24 status 3 ......................................................................................... 24 video processor .............................................................................. 25 sd luma path ............................................................................. 25 sd chroma path ......................................................................... 25 sync processing .......................................................................... 26 vbi data recovery ..................................................................... 26 general setup .............................................................................. 26 color controls ............................................................................ 28 clamp operation ........................................................................ 30 luma filte r .................................................................................. 31 chroma filter .............................................................................. 34 gain operation ........................................................................... 35 chroma transient improve ment (cti) .................................. 39 digital noise reduction (dnr) and luma peaking filter ... 40 comb filters ................................................................................ 41 if filter compensation ............................................................. 43 av code insertion and controls ............................................. 44 synchronization output signals ............................................... 46 sync processing .......................................................................... 53 vbi data decode ....................................................................... 53 i 2 c readback registers .............................................................. 62 pixel port configuration ............................................................... 75 gpo control ................................................................................... 76 mpu port description ................................................................... 77 register access ............................................................................ 78 register programming ............................................................... 78 i 2 c sequencer .............................................................................. 78 i 2 c register maps ........................................................................... 79 i 2 c programming examples ........................................................ 106 64- lead lqfp ........................................................................... 106 48- lead lqfp ........................................................................... 107 40- lead lfcsp ......................................................................... 108 32- lead lfcsp ......................................................................... 109 pcb layout recommendations .................................................. 110 analog interface inputs ........................................................... 110 power supply decoupling ....................................................... 110 pll ............................................................................................. 110 vrefn and vrefp ................................................................. 110 digital outputs (both data and cl ocks) .............................. 110 digital inputs ............................................................................ 110 typical circuit connection ......................................................... 111 outl ine dimensions ..................................................................... 115 ordering guide ........................................................................ 117 automotive products ............................................................... 117
data sheet adv7180 rev. g | page 3 of 120 revision history 3/12rev. f to rev. g changed adv7179 to adv7391 throughout ............................. 1 changes to figure 12 ...................................................................... 18 changes to table 14 ........................................................................ 19 changes to power-on reset section and man_mux_en, manual input muxing enable, address 0xc4[7] section .......... 20 changed ntsm to ntsc throughout ........................................ 24 deleted adv7190, adv7191, and adv7192 throughout ...... 27 change to def_c[7:0], default value c, address 0x0d[7:0] section .............................................................................................. 29 changes to luma filter section .................................................... 31 changes to table 39 and lagt[1:0], luma automatic gain timing, address 0x2f[7:6] section .............................................. 36 changed calculation of the luma calibration factor section heading to calculation of the chroma calibration factor section .............................................................................................. 38 changes to range, range selection, address 0x04[0] section .............................................................................................. 45 changes to phs, polarity hs, address 0x37[7] section ............ 46 changes to 0x0d, 0x1d, 0x2c, 0x37, and 0x41, table 107 ........ 85 changes to power supply decoupling section .........................110 deleted figure 55; renumbered sequentially ...........................110 changes to figure 55 ....................................................................111 changes to figure 56 ....................................................................112 changes to figure 57 ....................................................................113 changes to figure 58 ....................................................................114 changes to ordering guide .........................................................117 7/10rev. e to rev. f added 48-lead lqfp .................................................. throughout changes to features section ............................................................ 1 changes to table 2 ............................................................................ 4 added figure 5; renumbered sequentially ................................... 6 added input current (sda, sclk) parameter and input current ( pwrdwn ) parameter, table 3 ...................................... 7 added figure 11 and table 12; renumbered sequentially ........ 16 changes to man_mux_en, manual input muxing enable, address 0xc4[7] section ................................................................ 19 added gde_sel_old_adf bit description, table 107 ........ 92 moved 32-lead lfcsp section ...................................................108 added figure 58 ............................................................................112 updated outline dimensions ......................................................115 changes to ordering guide .........................................................116 2/10rev. d to rev. e added 32-lead lfcsp ................................................ throughout changes to features .......................................................................... 1 changes to figure 1 ........................................................................... 1 changes to introduction .................................................................. 4 added figure 4, renumbered sequentially ................................... 8 added figure 9 and table 11 ......................................................... 14 changes to figure 11 ...................................................................... 15 changes to table 12 and table 13 ................................................. 16 changes to power-on reset section, analog input muxing section, and table 14 ...................................................................... 17 changes to pdbp section and tod section .............................. 19 changes to identification section ................................................. 21 changes to vs and field configuration section and sqpe section .............................................................................................. 44 changes to table 99 and table 100 ............................................... 72 changes to gpo control section ................................................. 73 changes to table 104 ...................................................................... 76 changes to table 106 ...................................................................... 80 added figure 56 ............................................................................ 108 added figure 59 ............................................................................ 110 changes to ordering guide ......................................................... 110 6/09rev. c to rev. d change to general description ....................................................... 1 deleted comparison with the adv7181b section ...................... 5 deleted figure 2; renumbered sequentially ................................. 5 changes to power requirements parameter, table 2 ................... 6 changes to table 29 ........................................................................ 25 changes to figure 33 ...................................................................... 44 changes to subaddress 0x0a notes, table 104 ........................... 81 changes to ordering guide ......................................................... 110 4/09rev. b to rev. c changes to features section ............................................................ 1 changes to absolute maximum ratings, table 7 ....................... 11 changes to figure 7 and table 8, epad addition ...................... 12 added power-on reset section ................................................. 17 changes to man_mux_en, manual input muxing enable, address 0xc4[7] section and table 12......................................... 17 changes to identification section ................................................. 21 added table 16; renumbered sequentially ................................. 21 changes to table 21 ........................................................................ 23 changes to cil[2:0], count into lock, address 0x51[2:0] section and col[2:0], count out of lock, address 0x51[5:3] section .............................................................................................. 25 changes to table 32 and table 33 ................................................. 30 changes to table 34 ........................................................................ 32 changes to table 42 ........................................................................ 35 changes to table 52 ........................................................................ 38 changes to table 53 and table 56 ................................................. 39 changes to table 61 and figure 32 ............................................... 43 added sqpe, square pixel mode, address 0x01[2] section ..... 44 changes to newavmode, new av mode, address 0x31[4] section .............................................................................................. 44 changes to figure 34 ...................................................................... 45 changes to nftog[4:0], ntsc field toggle, address 0xe7[4:0] section ............................................................. 47 changes to pftog, pal field toggle, address 0xea[4:0] section .............................................................................................. 49 changes to vdp manuel configuration section ....................... 50 changes to table 66 ........................................................................ 51
adv7180 data sheet rev. g | page 4 of 120 changes to table 71 ........................................................................ 54 changes to table 72 ........................................................................ 55 changes to vps section and pdc/utc section ....................... 63 changes to gemstar_2x format, half-byte output mode section .............................................................................................. 66 changes to ntsc ccap data section and pal ccap data section .............................................................................................. 69 changes to figure 48 ...................................................................... 74 changes to i 2 c sequencer section ............................................... 75 changes to table 102 ...................................................................... 76 changes to table 104 ...................................................................... 80 changes to table 105 ...................................................................... 97 changes to figure 53 .................................................................... 108 changes to figure 54 .................................................................... 109 added exposed paddle notation to outline dimensions ...... 110 changes to ordering guide ........................................................ 111 2/07rev. a to rev. b changes to sfl_inv, subcarrier frequency lock inversion section .............................................................................................. 24 changes to table 103, register 0x41 ............................................ 90 updated outline dimensions ..................................................... 111 11/06rev. 0 to rev. a changes to table 10 and table 11 ................................................ 16 changes to table 30 ....................................................................... 28 changes to gain operation section ............................................ 33 changes to table 43 ....................................................................... 35 changes to table 97 ....................................................................... 72 changes to table 99 ....................................................................... 73 changes to table 103 ..................................................................... 80 changes to figure 54 .................................................................... 110 1/06revision 0: initial version
data sheet adv7180 rev. g | page 5 of 120 introduction the adv7180 is a versatile one - chip multiformat video decoder that automatically detects and converts pal, ntsc, and secam standar ds in the form of composite, s -v ideo, and component video into a digital itu - r bt.656 format. the simple digital output interface connects gluelessly to a wide range of mpeg encoders, codecs, mobile video processors, and analog devices digital video encoders, such as the adv7391 . external hs, vs, and field signals provide timing references for lcd controllers and other video asics that do not support the itu - r bt.656 interface standard. t he different package options available for the adv7180 are shown in table 2 . analog front end the adv7180 analog front end comprises a single high speed, 10- bit analog - to - digital converter (adc) that digitizes the analog video signal before applying it to the standard definition processor. the analog front end employs differential channels to the adc to ensure high performance in mixed - signal applications. the front end also includes a 3 - channel input mux that enables multiple composite video signals to be app lied to the adv7180. current clamps are positioned in front of the adc to ensure that the video signal remains within the range of the converter. a resistor divider network is required before each analog input channel to ensure that the input signal is kep t within the range of the adc (see figure 27 ). fine clamping of the video signal is performed downstream by digital fine clamping within the adv7180. table 1 shows the t hree adc clocking rates that are determined by the video input format to be processed that is, insel[3:0]. these clock rates ensure 4 oversampling per channel for cvbs mode and 2 oversampling per channel for y/c and yprpb modes. table 1 . adc clock rates input format adc clock rate (mhz) 1 oversampling rate per channel cvbs 57.27 4 y/c (s - video) 2 86 2 yprpb 86 2 1 based on a 28.6363 mhz crystal between the xtal and xtal1 pins. 2 see insel[3: 0 ] i n table 107 for the mandatory write for y/c (s -v ideo) mode. standard definition processor the adv7180 is capable of decoding a large selection of baseband video signals in composite, s -v ideo, and component formats. the video standards supp orted by the video processor include pal b/d/i/g/h, pal 60, pal m, pal n, pal nc, ntsc m/j, ntsc 4.43, and secam b/d/g/k/l. the adv7180 can automatically detect the video standard and process it accordingly. the adv7180 has a five - line, superadaptive, 2d c omb filter that gives superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user inte rvention. video user controls such as brightness, contrast, saturation, and hue are also available with the adv7180. the adv7180 implements a patented adllt? algorithm to track varying video line lengths from sources such as a vcr. adllt enables the adv718 0 to track and decode poor quality video sources such as vcrs and noisy sources from tuner outputs, v cd players, and camcorders. the adv7180 contains a chroma transient improvement (cti) processor that sharpens the edge rate of chroma transitions, resultin g in sharper vertical transitions. the video processor can process a variety of vbi data services, such as closed captioning (ccap), wide screen signaling (wss), copy generation management system (cgms), edtv, gemstar? 1/2, and extended data service (xd s). teletext data slicing for world standard teletext (wst), along with program delivery control (pdc) and video programming service (vps), are provided. data is transmitted via the 8 - bit video output port as ancillary data packets (anc). the adv7180 is fu lly macrovision? certified; detection circuitry enables type i, type ii, and type iii protection levels to be identified and reported to the user. the decoder is also fully robust to all macrovision signal inputs. table 2 . ad v7180 selection guide part number package type analog inputs digital outputs temperature grade adv7180kcp32z 32- lead lfcsp 3 8- bit ?10c to +70c adv7180wbcp32z (automotive) 1 32- lead lfcsp 3 8- bit ?40c to +85c adv7180bcpz 40- lead lfcsp 3 8- bit ?40c to +85c adv7180wbcpz (automotive) 1 40- lead lfcsp 3 8- bit ?40c to +125c adv7180bstz 64- lead lqfp 6 8- bit/16 - bit ?40c to +85c adv7180wbstz (automotive) 1 64- lead lqfp 6 8- bit/16 - bit ?40c to +125c adv7180wbst48z (automotive) 1 48- lead lqfp 6 8- bit ?4 0c to +85c 1 automotive qualification completed.
adv7180 data sheet rev. g | page 6 of 120 functional block dia grams 05700-055 a in 1 xtal1 xtal a in 2 a in 3 aa filter aa filter aa filter digital processing block 2d comb vbi slicer color demod sclk sdata alsb reset 10-bit, 86mhz adc reference pll adllt processing clock processing block i 2 c/control mux block fifo output block sha a/d hs llc vs/field intrq p7 to p0 8-bit pixel data sfl analog video inputs figure 2 . 32 - lead lfcsp functional diagram 05700-004 a in 1 xtal1 xtal a in 2 a in 3 aa filter aa filter aa filter digital processing block 2d comb vbi slicer color demod sclk sdata alsb reset pwrdwn 10-bit, 86mhz adc reference pll adllt processing clock processing block i 2 c/control mux block fifo output block sha a/d hs llc vs/field intrq p7 to p0 8-bit pixel data sfl analog video inputs figure 3 . 40 - lead lfcsp functional block diagram 05700-003 a in 1 a in 2 xtal1 xtal a in 3 a in 4 a in 5 a in 6 ana log video inputs aa fi lter aa fi lter aa fi lter d igi tal processing block 2d comb vbi slicer color demod sclk sda ta alsb reset pw rd wn 10 -bit, 86 mhz ad c refere nc e pll ad llt processing clo ck processing block i 2 c/control mux block fifo output block sha a/d hs llc vs sfl intrq p15 to p0 16 -bit pixel da ta field gpo0 t o g po3 figure 4 . 64 - lead lqfp functional block diagram
data sheet adv7180 rev. g | page 7 of 120 05700-060 a in 1 a in 2 xtal1 xtal a in 3 a in 4 a in 5 a in 6 analog video inputs aa filter aa filter aa filter digital processing block 2d comb vb i slicer color demod sclk sdata alsb reset pwrdwn 10-bit, 86mhz adc reference pll adllt processing clock processing block i 2 c/control mux block fifo output block sha a/d hs llc vs/field sfl intrq p7 to p0 8-bit pixel data gpo0 to gpo3 figure 5. 48 - lead lqfp functional block diagram
adv7180 data sheet rev. g | page 8 of 120 specifications electrical character istics a vdd = 1.71 v to 1.89 v, d vdd = 1.65 v to 2.0 v, d vddio = 1.62 v to 3.6 v, p vdd = 1.65 v to 2.0 v, specified at operating temperature range, unless otherwise noted. table 3. parameter symbol test conditions /comments min typ max unit static performance resolution (each adc) n 10 bits integral nonlinearity inl bsl in cvbs mode 2 lsb differential nonlinearity dnl cvbs mode ? 0.6/+0.6 lsb digital inputs input high voltage (dvddio = 3.3 v) v ih 2 v input high voltage (dvddio = 1.8 v) v ih 1.2 v input low voltage (dvddio = 3.3 v) v il 0.8 v input low voltage (dvddio = 1.8 v) v il 0.4 v crystal inputs v ih 1. 2 v v il 0.4 v input current i in ? 10 +10 a input current (sda, sclk) 1 i in ? 10 +1 5 a input current ( pwrdwn ) 2 i in ? 10 +40 a input capacitance c in 10 pf digital outputs output high voltage (dvddio = 3.3 v) v oh i source = 0.4 ma 2.4 v output high voltage (dvddio = 1.8 v) v oh i source = 0.4 ma 1.4 v output low voltage (dvddio = 3.3 v) v ol i sink = 3.2 ma 0.4 v output low voltage (dvddio = 1.8 v) v ol i sink = 1.6 ma 0.2 v high impedance leakage current i leak 10 a output capacitance c out 20 pf power requirements 3 , 4 , 5 digital power supply d vdd 1.65 1.8 2 v digital i/o power supply d vddio 1.62 3.3 3.6 v pll power supply p vdd 1.65 1.8 2.0 v analog power supply a vdd 1.71 1.8 1.89 v d igital supply current i dvdd 77 85 ma digital i/o supply current 6 i dvddio 3 5 ma pll supply current i pvdd 12 15 ma analog supply current i avdd cvbs input 33 43 ma y/c input 59 75 ma yprpb input 77 94 ma power - down current i dvdd 6 10 a i dvddio 0.1 1 a i pvdd 1 5 a i avdd 1 5 a total power dissipation in power - down mode 7 15 44 w power - up time t pwrup 20 ms 1 adv7180kcp32z, adv7180wbcp32z, and adv7180wbst48z only. 2 adv7180wbst48z only. 3 guaranteed by characterization. 4 typical current consumption values are recorded with nominal voltage supply levels and a smptebar p attern. 5 maximum current consumption values are recorded with maximum rated voltage supply levels and a multiburst pattern. 6 typical (typ) number is measured with dvddio = 3.3 v and maximum (max) number is measured with dvddio = 3.6 v. 7 adv7180 clocked.
data sheet adv7180 rev. g | page 9 of 120 video specifications gua ranteed by characterization. a vdd = 1.71 v to 1.89 v, d vdd = 1.65 v to 2.0 v, d vddio = 1.62 v to 3.6 v, p vdd = 1.65 v to 2.0 v, specified at operating temperature range, unless otherwise noted. table 4 . parameter symbol test conditions /comments min typ max unit nonlinear specifications differential phase dp cvbs input, modulate five - step [ntsc] 0.6 degrees differential gain dg cvbs input, modulate five - step [ntsc] 0.5 % luma nonlinearity lnl cvbs input, five - step [ntsc] 2.0 % noise specifications snr unweighted luma ramp 57.1 db luma fla t field 58 db analog front - end crosstalk 60 db lock time specifications horizontal lock range ?5 +5 % vertical lock range 40 70 hz f sc subcarrier lock range 1.3 khz color lock - in time 60 lines sync depth range 20 200 % color burst range 5 200 % vertical lock time 2 fields autodetection switch speed 100 lines chroma luma gain delay cvbs 2.9 ns y/c 5.6 ns yprpb ? 3.0 ns luma specifications luma brightness accuracy cvbs, 1 v input 1 % luma contrast accuracy cvbs, 1 v input 1 %
adv7180 data sheet rev. g | page 10 of 120 timing specification s gua ranteed by characterization. a vdd = 1.71 v to 1.89 v, d vdd = 1.65 v to 2.0 v, d vddio = 1.62 v to 3.6 v, p vdd = 1.65 v to 2.0 v, specified at operating temperature range, unless othe rwise noted. table 5 . parameter symbol test conditions min typ max unit system clock and crystal nominal frequency 28.6363 mhz frequency stability 50 ppm i 2 c port sclk frequency 400 khz sclk minimum pulse width high t 1 0.6 s sclk minimum pulse width low t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s sda setup time t 5 100 ns sclk and sda rise times t 6 300 ns sclk and sda fall times t 7 300 ns setup time for stop condition t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc mark space ratio t 9 :t 10 45:55 55:45 % duty cycle data and control outputs data output transitional time t 11 negative clo ck edge to start of valid data (t access = t 10 ? t 11 ) 3.6 ns data output transitional time t 12 end of valid data to negative clock edge (t hold = t 9 + t 12 ) 2.4 ns timing diagrams sdata sclk t 3 t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 05700-005 figure 6. i 2 c timing output llc outputs p0 t o p15, vs, hs, field, sfl t 9 t 10 t 11 t 12 05700-006 figure 7 . pixel port and control output timing
data sheet adv7180 rev. g | page 11 of 120 analog specification s gua ranteed by characterization. a vdd = 1.71 v to 1.89 v, d vdd = 1.65 v to 2.0 v, d vddio = 1.62 v to 3.6 v, p vdd = 1.65 v to 2.0 v, specified at operating temperature range, unless otherwise noted. table 6. parameter test conditions min typ max unit clamp circuitry external clamp capacitor 0.1 f input impedance clamps switched off 10 m? large - clamp source current 0.4 ma large - clamp sink current 0.4 ma fine clamp source current 10 a fine clamp sink current 10 a thermal specificatio ns table 7 . parameter symbol test conditions min typ max unit thermal characteristics junction -to - ambient thermal resistance (still air) ja 4- layer pcb with solid ground plane, 32 - lead lfcsp 32.5 c/w junction -to - case thermal resistance jc 4- layer pcb with solid ground plane, 32 - lead lfcsp 2.3 c/w jun ction -to - ambient thermal resistance (still air) ja 4- layer pcb with solid ground plane, 40 - lead lfcsp 30 c/w junction -to - case thermal resistance jc 4- layer pcb with solid ground plane, 40 - lead lfcsp 3 c/w junction -to - ambient thermal resistance ( still air) ja 4- layer pcb with solid ground plane, 64 - lead lqfp 47 c/w junction -to - case thermal resistance jc 4- layer pcb with solid ground plane, 64 - lead lqfp 11.1 c/w junction -to - ambient thermal resistance (still air) ja 4- layer pcb with soli d ground plane, 48 - lead lqfp 50 c/w junction -to - case thermal resistance jc 4- layer pcb with solid ground plane, 48 - lead lqfp 20 c/w
adv7180 data sheet rev. g | page 12 of 120 absolute maximum rat ings table 8 . parameter rating a vdd to agnd 2.2 v d vdd to dgnd 2 .2 v p vdd to agnd 2.2 v d vddio to dgnd 4 v d vddio to a vdd ?0.3 v to +4 v p vdd to d vdd ?0.3 v to +0.9 v d vddio to p vdd C 0.3 v to +4 v d vddio to d vdd ?0.3 v to +4 v a vdd to p vdd ?0.3 v to +0.3 v a vdd to d vdd ?0.3 v to +0.9 v digital inputs voltage d gnd ? 0.3 v to d vddi o + 0.3 v digital output s voltage dgnd ? 0.3 v to d vddi o + 0.3 v analog inputs to agnd agnd ? 0.3 v to a vdd + 0.3 v maximum junction temperature (t j max) 140c storage temperature range ?65c to +150c infrared reflow soldering (2 0 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational se ction of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance integrated circuit with an esd rating of <2 kv, and it is esd sensitive. prop er precautions should be taken for handling and assembly. esd caution
data sheet adv7180 rev. g | page 13 of 120 pin configurations and function descript ions 32- lead lfcsp 05700-057 notes 1. the exposedpad must be connectedto gnd. 1 2 3 4 5 6 7 8 hs dgnd dvddio sfl p7 p6 p5 p4 17 18 19 20 21 22 23 24 elpf pvdd a in 1 vrefp vrefn avdd a in 2 a in 3 pin1 indicator adv7180 lfcsp top view (not to scale) 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 p0 p1 dvdd xtal xtal1 llc p2 p3 reset alsb sdata sclk dgnd dvdd vs/field intrq figure 8 . 32 - lead lfcsp pin configuration table 9 . 32 - lead lfcs p pin function descriptions pin no. mnemonic type description 1 hs o horizontal synchronization output signal. 2, 29 dgnd g ground for digital supply. 3 dvddio p digital i/o supply voltage (1.8 v to 3.3 v). 4 sfl o subcarrier frequency lock. this p in contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any analog devices digital video encoder. 5 to 10, 15, 16 p7 to p2, p1, p0 o video pixel output port. 11 llc o line - locked output clock for the output pixel data. nominally 27 mhz but varies up or down according to video line length. 12 x tal1 o this pin should be connected to the 28.6363 mhz crystal or not connected if an external 1.8 v,28.6363 mhz clock oscillator source is used to clock the adv7180. in crystal mode, the crystal must be a fundamental crystal. 13 x tal i input pin for the 28.6363 mhz crystal. this pin can be overdriven by an external 1.8 v, 28.6363 mhz clock oscillator source. in crystal mode, the crystal must be a fundamental crystal. 14, 30 dvdd p digital supply voltage (1.8 v). 17 elpf i the recom mended external loop filter must be connected to this elpf pin, as shown in figure 58 . 18 pvdd p pll supply voltage ( 1.8 v). 19, 23, 24 a in 1 to a in 3 i analog video input channels. 20 vrefp o internal voltage reference output. see figure 58 for recommended output circuitry. 21 vrefn o internal voltage reference output. see figure 58 for recommended output circuitry. 22 avdd p analog supply voltage (1.8 v). 25 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7180 circuitry. 26 alsb i this pin selects the i 2 c address for the adv7180. for alsb set to logic 0, the address selected for a write is 0x40; for alsb set to logic 1, the address selected is 0x42. 27 sdata i/o i 2 c port serial data input /output pin. 28 sclk i i 2 c port serial clock input. the maximum clock rate is 400 khz. 31 vs/field o vertical synchronization output signal/field synchronization output signal. 32 intrq o interrupt request output. interrupt occurs when certain signals are detected on the input video (see table 108). epad (ep) the exposed pad must be connected to gnd.
adv7180 data sheet rev. g | page 14 of 120 40- lead lfcsp pin 1 indic at or 1 dvddio 2 sfl 3 dgnd 4 dvddio 5 p7 6 p6 7 p5 8 p4 9 p3 10 p2 23 a in 1 24 agnd 25 vrefp 26 vrefn 27 a vdd 28 agnd 29 a in 2 30 a in 3 notes 1. the exposed pad must be connected to gnd. 22 test_0 21 agnd 11 llc 12 xt al1 13 xtal 15 dgnd 17 p0 16 p1 18 pwrdwn 19 elpf 20 pvdd 14 dvdd 33 sdat a 34 sclk 35 dgnd 36 dvdd 37 vs/field 38 intrq 39 hs 40 dgnd 32 alsb 31 reset lfcs p top view (not to scale) adv7180 05700-007 figure 9 . 40 - lead lfcsp pin configur ation table 10 . 40- lead lfcsp pin function descriptions pin no. mnemonic type description 1, 4 dvddio p digital i/o supply voltage (1.8 v to 3.3 v). 2 sfl o subcarrier frequency lock. this pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any analog devices digital video encoder. 3, 15, 35, 40 dgnd g ground for digital supply. 5 to 10, 16, 17 p7 to p2, p1, p0 o video pixel output port. 11 llc o line - locked output clock for the outp ut pixel data. nominally 27 mhz but varies up or down according to video line length. 12 x tal1 o this pin should be connected to the 28.6363 mhz crystal or not connected if an external 1.8 v, 28.6363 mhz clock oscillator source is used to clock the adv7180. in crystal mode, the crystal must be a fundamental crystal. 13 x tal i input pin for the 28.6363 mhz crystal. this pin can be overdriven by an external 1.8 v, 28.6363 mhz clock oscillator source. in crystal mode, the crystal must be a fundamental crystal. 14, 36 dvdd p digital supply voltage (1.8 v). 18 pwrdwn i a logic low on this pin places the adv7180 into power - down mode. 19 elpf i the recom mended external loop filter must be connect ed to this elpf pin, as shown in figure 55 . 20 pvdd p pll supply voltage (1.8 v). 21, 24, 28 agnd g ground for analog supply. 22 test_0 i this pin must be tied to dgnd. 23, 29, 30 a in 1 to a in 3 i analog vi deo input channels. 25 vrefp o internal voltage reference output. see figure 55 for recommended output circuitry. 26 vrefn o internal voltage reference output. see fi gure 55 for recommended output circuitry. 27 avdd p analog supply voltage (1.8 v). 31 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7180 circuitry. 32 alsb i th is pin selects the i 2 c address for the adv7180. for alsb set to logic 0, the address selected for a write is 0x40; for alsb set to logic 1, the address selected is 0x42. 33 sdata i/o i 2 c port serial data input/output pin. 34 sclk i i 2 c port serial c lock input. the maximum clock rate is 400 khz. 37 vs/field o vertical synchronization output signal/field synchronization output signal. 38 intrq o interrupt request output. interrupt occurs when certain signals are detected on the input video (see table 108). 39 hs o horizontal synchronization output signal. epad (ep) the exposed pad must be connected to gnd.
data sheet adv7180 rev. g | page 15 of 120 64- lead lqfp 64 vs 63 field 62 p12 61 p13 60 p14 59 p15 58 dvdd 57 dgnd 56 gpo2 55 gpo3 54 sclk 53 sd at a 52 alsb 51 reset 50 nc 49 a in 6 47 a in 4 46 a in 3 45 nc 42 nc 43 agnd 44 nc 48 a in 5 41 nc 40 avdd 39 vrefn 37 agnd 36 a in 2 35 a in 1 34 test_0 33 nc 38 vrefp 2 hs 3 dgnd 4 d vdd io 7 p9 6 p10 5 p11 1 intrq 8 p8 9 sfl 10 dgnd 12 gpo1 13 gpo0 14 p7 15 p6 16 p5 11 d vdd io 17 p4 18 p3 19 p2 20 llc 21 xt al1 22 xtal 23 dvdd 24 dgnd 25 p1 26 p0 27 nc 28 nc 29 pwrdwn 30 elpf 31 pvdd 32 agnd pin 1 adv 7180 lqfp top view (not to s ca le) nc = no co nn ect 05700-008 figure 10 . 64 - lead lqfp pin configuration table 11 . 64- lead lqfp pin function description pin no. mnemonic type description 1 intrq o interrupt request output. interrupt occurs when certain signals are detected on the input video (s ee table 108). 2 hs o horizontal synchronization output signal. 3, 10, 24, 57 dgnd g digital ground. 4, 11 dvddio p digital i/o supply voltage (1.8 v to 3.3 v). 5 to 8, 14 to 19, 25, 26, 59 to 62 p11 to p8, p7 to p2, p1, p0, p15 to p12 o video pixel output port. see table 100 for output configuration for 8 - bit and 16- bit modes. 9 sfl o subcarrier frequency lock. this pin contains a serial output strea m that can be used to lock the subcarrier frequency when this decoder is connected to any analog devices digital video encoder. 12, 13, 55, 56 gpo0 to gpo3 o general - purpose outputs. these pins can be configured via i 2 c to allow control of external devic es. 20 llc o this is a line - locked output clock for the pixel data output by the adv7180. it is nominally 27 mhz but varies up or down according to video line length. 21 x tal1 o this pin should be connected to the 28.6363 mhz crystal or left as a no connect if an external 1.8 v, 28.6363 mhz clock oscillator source is used to clock the adv7180. in crystal mode, the crystal must be a fundamental crystal. 22 x tal i this is the input pin for the 28.6363 mhz crystal, or this pin can be overdriven by an external 1.8 v, 28.6363 mhz clock oscillator source. in crystal mode, the crystal must be a fundamental crystal. 23, 58 dvdd p digital supply voltage (1.8 v). 27, 28, 33, 41, 42, 44, 45, 50 nc no connect . these pins are not connected internally. 29 pwrdwn i a logic low on this pin places the adv7180 in power - down mode. 30 elpf i the recommended external loop filter must be connected to the elpf pin, as shown in figure 56 . 31 pvdd p pll supply voltage (1.8 v). 32, 37, 43 agnd g analog ground. 34 test_0 i this pin must be tied to dgnd. 35, 36, 46 to 49 a in 1 to a in 6 i analog video input channels.
adv7180 data sheet rev. g | page 16 of 120 pin no. mnemonic type description 38 vrefp o internal voltage reference output. see figure 56 for recommended output circuitry. 39 vrefn o internal voltage reference output. see figure 56 for recommended output circuitry. 40 avdd p analog supply voltage (1.8 v). 51 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7180 circuitry. 52 alsb i this pin selects the i 2 c address for the adv7180. for alsb set to logic 0, the address selected for a write is 0x40; for alsb set to logic 1, the address selected is 0x42. 53 sdata i/o i 2 c port serial data input/output pin. 54 sclk i i 2 c port serial clock input. the maximum clock rate is 400 khz. 63 field o field synchronization output s ignal. 64 vs o vertical synchronization output signal.
data sheet adv7180 rev. g | page 17 of 120 48- lead lqfp 48 nc 47 hs 46 intrq 45 vs/field 44 dvdd 43 dgnd 42 gpo2 41 gpo3 40 sclk 39 sdat a 38 alsb 37 reset 35 a in 5 34 a in 4 33 a in 3 30 vfefn 31 a vdd 32 agnd 36 a in 6 29 vrefp 28 agnd 27 a in 2 25 pvdd 26 a in 1 2 dvddio 3 sfl 4 dvddio 7 p7 6 gpo0 5 gpo1 1 dgnd 8 p6 9 p5 10 p4 12 p2 11 p3 nc = no connect 13 dgnd 14 llc 15 nc 16 xt al1 17 xtal 18 dvdd 19 dgnd 20 p1 21 pwrdwn 22 p0 23 agnd 24 elpf pin 1 adv7180 lqf p top view (not to scale) 05700-062 figure 11 . 48 - lead lqfp pin configuration table 12. 48- lead lqfp pin function descriptions pin no. mnemonic type description 1, 13, 19, 43 dgnd g digital ground. 2, 4 dvddio p digital i/o supply voltage (1.8v to 3.3 v). 3 sfl o subcarrier frequency lock. this pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any analog devices digital video encoder. 5, 6, 41, 42 gpo0 to gpo3 o general - purpose outputs. these pins can be configured via i 2 c to allow control of external devices. 7 to 12, 20, 22 p7 to p2, p1, p0 o video pixel output port. see table 100 for output configuration for 8 - bit and 16- bit modes. 14 llc o this is a line - locked output clock for the pixel data output by the adv7180. it is nominally 27 mhz but varies up or down according to video line le ngth. 15, 48 nc no connect pins. these pins are not connected internally. 16 x tal1 o this pin should be connected to the 28.6363 mhz crystal or left as a no connect if an external 1.8 v, 28.6363 mhz clock oscillator source is used to clock the adv7180 . in crystal mode, the crystal must be a fundamental crystal. 17 x tal i this is the input pin for the 28.6363 mhz crystal, or this pin can be overdriven by an external 1.8 v, 28.6363 mhz clock oscillator source. in crystal mode, the crystal must be a f undamental crystal. 18, 44 dvdd p digital supply voltage (1.8 v). 21 pwrdwn i a logic low on this pin places the adv7180 in power - down mode. 23, 28, 32 agnd g analog ground. 24 elpf i the recommended external loop filter m ust be connected to the elpf pin, as shown in figure 57 . 25 pvdd p pll supply voltage (1.8 v). 26, 27, 33 to 36 a in 1 to a in 6 i analog video input channels. 29 vrefp o internal voltage reference output. see figure 57 for recommended output circuitry. 30 vrefn o internal voltage reference output. see figure 57 for recommended output circuitry. 31 avdd p analog supply vol tage (1.8 v). 37 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7180 circuitry. 38 alsb i this pin selects the i 2 c address for the adv7180. for alsb set to logic 0, the address selected for a write is 0x40; for alsb set to logic 1, the address selected is 0x42. 39 sdata i/o i 2 c port serial data input/output pin. 40 sclk i i 2 c port serial clock input. the maximum clock rate is 400 khz. 45 vs/field o vertical s ynchronization output signal/field synchronization output signal. 46 intrq o interrupt request output. interrupt occurs when certain signals are detected on the input video (see table 1 08 ). 47 hs o horizontal synchronization output signal.
adv7180 data sheet rev. g | page 18 of 120 analog front end a in 2 a in 1 a in 4 a in 3 a in 6 a in 5 a in 5 a in 6 a in 3 a in 4 a in 1 a in 2 a in 4 a in 3 a in 6 a in 5 a in 6 a in 2 a in 5 man_mux_en mux_0[2:0] mux_1[2:0] mux_2[2:0] 05700-009 adc figure 12 . 64 - lead and 48 - lead lqfp internal pin connections a in 1 a in 2 a in 3 a in 3 a in 2 a in 1 a in 2 a in 3 a in 3 man_mux_en mux_0[2:0] mux_1[2:0] mux_2[2:0] 05700-010 adc figure 13 . 40 - lead and 32 - lead lfcsp internal pin connection s
data sheet adv7180 rev. g | page 19 of 120 input configuration the following are the two key steps for configuring the adv7180 to correctly decode the input video: 1. use insel[3:0] to configure the routing and format decoding (cvbs, y/c, or yprpb). for the 64 -lead and 48 -lead l q f p, see table 13 . for the 40 - lead and 32 - lead lfcsp, see table 14 . 2. if the input requirements are not met using the insel[3:0] options, the analog input muxing section must b e configured manually to correctly route the video from the analog input pins to the adc. the standard definition processor block, which decodes the digital data, should be configured to process the cvbs, y/c, or yprpb format. this is performed by insel[3:0] selection. connect analog video signals to adv7180. set insel[3:0] to configure video format. use predefined format/routing. configure adc inputs using manual muxing control bits: mux_0[2:0], mux_1[2:0], mux_2[2:0]. see table 15. refer to table 13 refer to table 14 lqfp-64 lqfp-48 lfcsp-40 lfcsp-32 05700-011 no yes figure 14 . signal routing options insel[3:0], input selection, address 0x00[3:0] the insel bits allow the user to select the input format. they also configure the standard definition processor core to process c ompos ite (cvbs), s -v ideo (y/c), or component (yprpb) format. insel[3:0] has predefined analog input routing schemes that do not require manual mux programming (see table 13 and table 14 ). this allows the user to route the various video signal types to the decoder and select them using insel[3:0] only. the added benefit is that if, for example, the cvbs input is selected, the remaining channels are powered down. table 13 . 64- lead and 48 - lead lqfp insel[3:0] insel[3:0] video format analog input 0000 composite cvbs input on a in 1 0001 composite cvbs input on a in 2 0010 composite cvbs input on a in 3 0011 composite cvbs input on a in 4 0100 composite cvbs input on a in 5 0101 composite cvbs input on a in 6 0110 y/c (s -v ideo) y input on a in 1 c input on a in 4 0111 y/c (s -v ideo) y input on a in 2 c input on a in 5 1000 y/c (s -v ideo) y input on a in 3 c input on a in 6 1001 yprpb y input on a in 1 pb input o n a in 4 pr input on a in 5 1010 yprpb y input on a in 2 pr input on a in 6 pb input on a in 3 1011 to 1111 reserved reserved table 14 . 40- lead and 32 - lead lfcsp insel[3:0] insel[3:0] video format analog input 0000 composite cvbs input on a in 1 0001 to 0010 reserved reserved 0011 composite cvbs input on a in 2 0100 composite cvbs input on a in 3 0101 reserved reserved 0110 y/c (s -v ideo) y input on a in 1 c input on a in 2 0111 to 1000 reserved reserved 1001 yprpb y input on a in 1 pr input on a in 3 pb input on a in 2 1010 to 1111 reserved reserved
adv7180 data sheet rev. g | page 20 of 120 power - on reset after power - up, it is necessary to execute a reset operation. for correct operation, reset should remain asserted /pulled low fo r 5 ms after power supplies are stable and within specification and pwrdwn ( not available in 32 - lead lfcsp ) is de asserted / pulled high . analog input muxing the adv7180 has an integrated analog muxing section that allows more than one so urce of video signal to be connected to t he decoder. figure 12 and figure 13 outline the overall structure of the input muxing provided in the adv7180 . a maximum of six c vbs inputs can be connected to and decoded b y the 64 -l ead and 48 -lead device s, and a maximum of three cvbs inputs can be connected to and decoded by the 40 - lead and 32 - lead lfcsp devices. as shown in the pin conf igurations and function description section, these analog input pins lie in close proximity to one another, which requires careful design of the printed circuit board ( pcb ) layout. for example, ground shielding between all signals should be routed through tracks that are physically close together. it is strongly recommended to connect any unused analog input pins to agnd to act as a shield. man_mux_en, manual input muxing enable, address 0xc4[7] to configure the adv7180 analog muxing section, the user mu st select the analog input (a in 1 to a in 6 for the 64 -l ead lqfp and 48 - lead device s or a in 1 to a in 3 for the 40- lead and 32 -l ead lfcsp devices) that is to be processed by the adc. man_mux_ en must be set to 1 to enable the following muxing blocks: ? mux0[2:0] , adc mux configuration, address 0xc3[2:0] ? mux1[ 2:0 ], adc mux configuration, address 0xc3[ 6: 4] ? mux2[2:0], adc mux configuration, address 0xc4[2:0] the three mux sections are controlled by the signal buses mux0/ mux1/mux2[ 2:0]. table 15 explains the control words used. the input signal that contains the timing information (hs and vs) must be processed by mux0. for example, in a y/c input configuration, mux0 should be connected to the y channel and mux1 to the c ch annel. when one or more muxes are not used to process video, such as the cvbs input, the idle mux and associated channel clamps and buffers should be powered down (see the description of register 0x3a in table 107 ). table 15 . manual mux settings for the adc (man_mux_en must be set to 1) adc connected t o adc connected t o adc connected t o mux0[2:0] lqfp - 64 or lqfp - 48 lfcsp - 40 or lfcsp - 32 mux1[2:0] lqfp - 64 or lqfp - 48 lfcsp - 40 or lfcsp - 32 mux2[2:0] lqfp - 64 or lqfp - 48 lfcsp - 40 or lfcsp - 32 000 no connect no connect 000 no connect no connect 000 no connect no connect 001 a in 1 a in 1 001 no connect no connect 001 no connect no connect 010 a in 2 no connect 010 no connect no connect 010 a in 2 no c onnect 011 a in 3 no connect 011 a in 3 no connect 011 no connect no connect 100 a in 4 a in 2 100 a in 4 a in 2 100 no connect no connect 101 a in 5 a in 3 101 a in 5 a in 3 101 a in 5 a in 3 110 a in 6 no connect 110 a in 6 no connect 110 a in 6 no connect 111 no connect no conn ect 111 no connect no connect 111 no connect no connect note the following: ? cvbs can only be processed by mux0. ? y/c can only be processed by mux0 and mux1 . ? yprpb can only be processed by mux0, mux1, and mux2.
data sheet adv7180 rev. g | page 21 of 120 antialiasing filters the adv7180 has option al on - chip antialiasing (aa) filters on each of the three channels that are multiplexed to the adc (see figure 15 ). the filters are designed for standard definition video up to 10 mhz bandwidth. figure 16 and figure 17 show the filter magnit ude and phase characteristics. the antialiasing filters are enabled by default and the selection of insel[3:0] determines which filters are powered up at any given time. for example, if cvbs mode is selected, the filter circuits for the remaining input channels are powered down to conserve power. however, the antialiasing filters can be disabled or bypassed using the aa_filt_man_ovr contro l. a in 1 a in 2 a in 3 a in 4 1 a in 5 1 a in 6 1 aa filter 1 aa filter 2 aa filter 3 10-bit, 86mhz adc mux block sha a/d 05700-012 1 only available in 64-lead and 48-lead packages. figure 15 . antialias filter configuration aa_filt_man_ovr, antialiasing filter override, address 0xf3[3] this feature allows the user to override the antialiasing filters on/off settings, which are automatically selected by in sel[3:0]. aa_filt_en, antialiasing filter enable, address 0xf3[2:0] these bits allow the user to enable or disable the antialiasing filters on each of the three input channels multiplexed to the adc. when disabled, the analog signal bypasses the aa filter and is routed directly to the adc. aa_filt_en, address 0xf3[0] when aa_filt_en[0] is 0, aa filter 1 is bypassed. when aa_filt_en[0] is 1, aa filter 1 is enabled. aa_filt_en, address 0xf3[1] when aa_filt_en[1] is 0, aa filter 2 is bypassed. when aa_filt_e n[1] is 1, aa filter 2 is enabled. aa_filt_en, address 0xf3[2] when aa_filt_en[2] is 0, aa filter 3 is bypassed. when aa_filt_en[2] is 1, aa filter 3 is enabled. 0 ?36 1k 100m 05700-013 frequency (hz) magnitude (db) 10k 100k 1m 10m ?4 ?8 ?12 ?16 ?20 ?24 ?28 ?32 figure 16 . antialiasing filter magnitude response 0 ?150 1k 100m 05700-014 frequency (hz) 10k 100k 1m 10m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 phase (degrees) figure 17 . antialiasing filter phase response
adv7180 data sheet rev. g | page 22 of 120 global control regis ters register control bits listed in this section affect the whole chip. power - saving modes power - down pdbp, address 0x0f[2] the digital supply of the adv7180 can be shut down by using the pwrdwn pin or via i 2 c 1 (s ee the pwrdwn, address 0x0f[5] section). pdbp controls whether the i 2 c control or the pin has the higher priority. the default is to give the pin ( pwrdwn ) priority 2 . this allows the user to have the adv7180 powered down by default at power - up without the need for an i 2 c write. when pdbp is 0 (default), the digital supply power is controlled by the pwrdwn pin 2 (the pwrdwn bit, 0x0f[5], is disregarded). when pdbp is 1, the pwrdwn bit has priority (the pin is disregarded). pwrdwn, address 0x0f[5] when pdbp is set to 1, setting the pwrdwn bit switches the adv7180 to a chip - wide power - down mode. the power - down stops the clock from entering the digital section of the chip, thereby freezing its operation. no i 2 c bits are lost during power - down. the pwrdwn bit also affects the analog blocks and switches them into low curren t modes. the i 2 c interface is unaffected and remains operational in power - down mode. the adv7180 leaves the power - down state if the pwrdwn bit is set to 0 (via i 2 c) or if the adv7180 is reset using the reset pin. pdbp must be set to 1 for the pwrdwn bit to power down the adv7180 . when pwrdwn is 0 (default), the chip is operational. when pwrdwn is 1, the adv7180 is in a chip - wide power - down mode. reset control reset, chip reset, address 0x0f[7] setting this bit, which is equivalent t o controlling the reset pin on the adv7180, issues a full chip reset. all i 2 c registers are reset to their default/power - up values. note that some register bits do not have a reset value specified. they keep their last written value. those bits are marked as having a reset value of x in the register tables (see table 107 and table 108 ). after the reset sequence, the part immediately starts to acquire the incoming video signal. 1 for 32 - lead , i 2 c is the only power - down option. 2 for 64 - lead, 48 -l ead , and 40 - lead only. after setting the reset bit (or initiating a reset via the reset pin), the part returns to the default for its primary mode of operation. all i 2 c bits are loaded with their default values, making this bi t self-clearing. executing a software reset takes approximately 2 ms. however, it is recommended to wait 5 ms before any further i 2 c writes are performed. the i 2 c master controller receives a no acknowledge condition on the ninth clock cycle when chip res et is impleme nted (s ee the mpu port description section ). when the reset bit is 0 (default), operation is normal. when the reset bit is 1, the reset sequence starts. global pin control three - state output drive rs tod, address 0x03[6] this bit allows the user to three - state the output drivers of the adv7180. upon setting the tod bit, the p15 to p0 (p7 to p0 for the 48 - lead, 40 -l ead , and 32 -l ead devices), hs, vs, field (vs/field pin for the 48 -lead, 40 -lead, and 3 2-l ead lfcsp), and sfl pins are three - stated. the timing pins (hs, vs, field) can be forced active via the tim_oe bit. for more information on three - state control, see the three - state llc driver and the timing signals output enable sections. individual drive strength controls are provided via the dr_str_ x bits. when tod is 0 (default), the output drivers are enabled. when tod is 1, the output drivers are three - stated. three - state llc driver tri_llc, address 0x1d[7] this bit allows the output drivers for the llc pin of the adv7180 to be three - stated. for more information on three - state control, refer to the three - state output d rivers and the timing signals output enable sections. individual drive strength controls are provided via the dr_str_ x bits. when tri_llc is 0 (default), the llc pin drivers work according to the dr_str_c[1:0] s etting (pin enabled). when tri_llc is 1, the llc pin drivers are three - stated.
data sheet adv7180 rev. g | page 23 of 120 timing signals output enable tim_oe, address 0x04[3] the tim_oe bit should be regarded as an addition to the tod bit. setting it high forces the output drivers for hs, vs , and field into the active state (that is, driving state) even if the tod bit is set. if tim_oe is set to low, the hs, vs, and field pins are three - stated depending on the tod bit. this functionality is beneficial if the decoder is only used as a timing g enerator. this may be the case if only the timing signals are extracted from an incoming signal or if the part is in free - run mode, where a separate chip can output a company logo, for example. for more information on three - state control, see the three - state output drivers section and the three - state llc driver section. individual drive strength controls are provided via the dr_str_ x bits. when tim_oe is 0 (default), hs, vs, and field are three - stated according to the tod bit. when tim_oe is 1, hs, vs, and field are forced active all the time. drive strength selection (data) dr_str[1:0], address 0xf4[5:4] for emc and crosstalk reasons, it may be desirable to strengthe n or weaken the drive strength of the output drivers. the dr_str[1:0] bits affect the p[15:0] for the 64 -l ead device or p[7:0] for the 48 -lead, 40 -l ead , and 32 -l ead devices output drivers. for more information on three - state control, see the drive strength selection (clock) and the drive strength selection (sync) sections. table 16 . dr_str function dr_str[1:0] description 00 low drive strength (1) 01 (default) medium low drive strength (2) 10 medium high drive strength (3) 11 high drive strength (4) drive strength selection (clock) dr_str_c[1:0], address 0xf4[3:2] the dr_str_c[1:0] bits can be used to select the strength of the clock si gnal output driver (llc pin). for more information, see the drive strength selection (sync) and the drive strength selection (data) sections. table 17 . dr_str_c function dr_str_c[1:0] description 00 low drive strength (1) 01 (default) medium low drive strength (2) 10 medium high drive strength (3) 11 high drive strength (4) drive strength selection (sync) dr_str_s[1:0], address 0xf4[1:0] the dr_str_s[1:0] bits allow the user to select the strength of the synchronization signals with which hs, vs, and field are driven. for more information, see the drive strength selection (data) section. tabl e 18 . dr_str_s function dr_str_s[1:0] description 00 low drive strength (1) 01 (default) medium low drive strength (2) 10 medium high drive strength (3) 11 high drive strength (4) enable subcarrier frequency lock pin en_sf l_pin, address 0x04[1] the en_sfl_pin bit enables the output of subcarrier l ock information (also known as g enlock) from the adv7180 core to an encoder in a decoder/encoder back - to - back arrangement. when en_sfl_pin is 0 (default), the subcarrier frequency lock output is disabled. when en_sfl_pin is 1, the subcarrier frequency lock information is presented on the sfl pin. polarity llc pin pclk, address 0x37[0] the polarity of the clock that leaves the adv7180 via the llc pin can be inverted using the pclk bi t. changing the polarity of the llc clock output may be necessary to meet the setup - and - hold time expectations of follow - on chips. when pclk is 0, the llc output polarity is inverted. when pclk is 1 (default), the llc output polarity is normal (see the timing specifications section).
adv7180 data sheet rev. g | page 24 of 120 global status regist er four registers provide summary information about the video decoder. the ident register allows the user to identify the revision code of the adv7180. the ot her three registers (0x10, 0x12, and 0x13) contain status bits from the adv7180. identification ident[7:0], address 0x11[7:0] this is the register identification of the adv7180s revision. table 19 describes the various versions of the adv7180. table 19 . ident code ident[7:0] description 0x1b 1 initial release silicon 0x1c 1 improved esd and pdc fix 0x1e 48- lead and 32 - lead device s only 1 64- lead and 40 - lead models only. status 1 status 1[7:0], address 0x10[7:0] this read - only register provides information about the internal status of the adv7180. see the cil[2:0], count into lock, address 0x51[2:0] section and the col[2:0], count out of lock, address 0x51[5:3] section for details on timing. depending on the setting of the fscle bit, the status register 0 and status register 1 are based solely on horizontal timing information or on the horizontal timin g and lock status of the color subcarrier. see the fscle, f sc lock enable, address 0x51[7] section. autodetection result ad_result[2:0], address 0x10[6:4] the ad_result[2:0] bits report back on the findings from the adv7180 autodetection block. see the general setup section for more information on enabling the autodetection block and the autodetection of sd modes section for more information on how to configure it. table 20 . ad_result function ad_result[2:0] description 000 ntsc m/j 001 ntsc 4.43 010 pal m 011 pal 60 100 pal b/g/h/i/d 101 secam 110 pal combination n 111 secam 525 table 21 . status 1 function status 1[7:0] bit name description 0 in_lock in lock (now) 1 lost_lock lost lock (since last read of this register) 2 fsc_lock f sc locked (now) 3 follow_pw agc follows peak white algorithm 4 ad_result[0] r esult of autodetection 5 ad_result[1] result of autodetection 6 ad_result[2] result of autodetection 7 col_kill color kill active status 2 status 2[7:0], address 0x12[7:0] table 22 . status 2 function status 2[7:0] bit name desc ription 0 mvcs det detected macrovision color striping 1 mvcs t3 macrovision color striping protection; conforms to type 3 if high, type 2 if low 2 mv ps det detected macrovision pseudo - sync pulses 3 mv agc det detected macrovision agc pulses 4 ll nst d line length is nonstandard 5 fsc nstd f sc frequency is nonstandard 6 reserved 7 reserved status 3 status 3[7:0], address 0x13[7:0] table 23 . status 3 function status 3[7:0] bit name description 0 inst_hlock horizontal loc k indicator (instantaneous) 1 gemd gemstar detect 2 sd_op_50hz flags whether 50 hz or 60 hz is present at output 3 reserved reserved for future use 4 free_run_act adv7180 outputs a blue screen (see the def_val _en, default value enable, address 0x0c[0] section) 5 std fld len field length is correct for currently selected video standard 6 interlaced interlaced video detected (field sequence found) 7 pal_sw_lock reliable sequence of swinging bursts detected
data sheet adv7180 rev. g | page 25 of 120 video processor digitized cvbs digitized y (yc) video data output standard definition processor digitized cvbs digitized c (yc) macrovision detection vbi data recovery standard autodetection luma filter luma digital fine clamp luma gain control luma resample luma 2d comb sllc control chroma filter chroma demod f sc recovery chroma digital fine clamp chroma gain control chroma resample chroma 2d comb sync extract line length predictor resample control av code insertion measurement block ( i 2 c) video data processing block 05700-015 figure 18 . block diagram of the video processor figure 18 shows a block diagram of the adv7180 video processor. the adv7180 can handle standard definition video i n cvbs, y/c, and yprpb formats. it can be divided into a luminance and chrominance path. if the input video is of a composite type (cvbs), both processing paths are fed with the cvbs input. sd luma path the input signal is processed by the following blocks : x luma digital fine clamp. this block uses a high precision algorithm to clamp the video signal. x luma f ilter. this block contains a luma decimation filter (yaa) with a fixed response and some shaping filters (ysh) that have selectable responses. x luma gai n control. the automatic gain control (agc) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. x luma resample. to correct for line length errors as well as dy namic line length changes, the data is digitally resampled. x luma 2d comb. the 2d comb filter provides y/c separation. x av code insertion. at this point, the decoded luma (y) signal is merged with the retrieved chroma values. av codes can be inserted (as p er itu - r bt.656). sd chroma path the input signal is processed by the following blocks: x chroma digital fine clamp. this block uses a high precision algorithm to clamp the video signal. x chroma demodulation. this block employs a color subcarrier (f sc ) rec overy unit to regenerate the color subcarrier for any modulated chroma scheme. the demodulation block then performs an am demodulation for p al and ntsc, and an fm demodulation for secam. x chroma filter. this block contains a chroma decimation filter (caa) with a fixed response and some shaping filters (csh) that have selectable responses. x chroma gain control. agc can operate on several different modes, including gain based on the color subcarrier amplitude, gain based on the depth of the horizontal sync pu lse on the luma channel, or fixed manual gain. x chroma resample. the chroma data is digitally resampled to keep it perfectly aligned with the luma data. the resampling is done to correct for static and dynamic line length errors of the incoming video signa l. x chroma 2d comb. the 2d, five line, superadaptive comb filter provides high quality y/c separation in case the input signal is cvbs. x av code insertion. at this point, the demodulated chroma (cr and cb) signal is merged with the retrieved luma values. av codes can be inserted (as per itu - r bt.656).
adv7180 data sheet rev. g | page 26 of 120 sync processing the adv7180 extracts syncs embedded in the analog input video signal. there is currently no support for external hs/vs inputs. the sync extraction is optimized to support imperfect video sources, such as vcrs with head switches. the actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. the raw sync information is sent to a line length measure ment and prediction block. the output of this is then used to drive the digital resampling section to ensure that the adv7180 outputs 720 active pixels per line. the sync processing on the adv7180 also includes the following specialized postprocessing blo cks that filter and condition the raw sync information retrieved from the digitized analog video: ? vsync processor. this block provides extra filtering of the detected vsyncs to improve vertical lock. ? hsync processor. the hsync processor is designed to filt er incoming hsyncs that have been corrupted by noise, providing much improved performance for video signals with a stable time base but poor snr. vbi data recovery the adv7180 can retrieve the following information from the input video: ? wide screen signali ng (wss) ? copy generation management system (cgms) ? closed captioning (ccap) ? macrovision protection presence ? edtv data ? gemstar - compatible data slicing ? teletext ? vitc/vps the adv7180 is also capable of automatically detecting the incoming video standard with respect to ? color subcarrier frequency ? field rate ? line rate the adv7180 can configure itself to support pal b/d/i/g/h, pal m, pal n, pal combination n, ntsc m, ntsc j, secam 50 hz/60 hz, ntsc 4.43, and pal 60. general setup video standard selection th e vid_sel[3:0] bits (address 0x00[7:4]) allow the user to force the digital core into a specific video standard. under normal circumstances, this is not necessary. the vid_sel[3:0] bits default to an auto detection mode that supports pal, ntsc, secam, and v ariants thereof. autodetection of sd modes to guide the autodetect system of the adv7180, individual enable bits are provided for each of the supported video standards. setting the relevant bit to 0 inhibits the standard from being detected automatically. instead, the system chooses the closest of the remaining enabled standards. the results of the autodetection block can be read back via the status registers (s ee the global status register section for more info rmation ). vid_sel[3:0], address 0x00[7:4] table 24 . vid_sel function vid_sel[3:0] description 0000 (default) autodetect (pal b/g/h/i/d), ntsc j (no pedestal), secam 0001 autodetect (pal b/g/h/i/d), ntsc m (pedestal), secam 0010 autodetec t (pal n) (pedestal) , ntsc j (no pedestal), secam 0011 autodetect (pal n) (pedestal), ntsc m (pedestal), secam 0100 ntsc j 0101 ntsc m 0110 pal 60 0111 ntsc 4.43 1000 pal b/g/h/i/d 1001 pal n = pal b/g/h/i/d (with pedestal) 1010 pal m ( without pedestal) 1011 pal m 1100 pal combination n 1101 pal combination n (with pedestal) 1110 secam 1111 secam (with pedestal) ad_sec525_en, enable autodetection of secam 525 line video, address 0x07[7] setting ad_sec525_en to 0 (default) disables the autodetection of a 525 - line system with a secam style, fm - modulated color component. setting ad_sec525_en to 1 enables the detection of a secam style, fm - modulated color component.
data sheet adv7180 rev. g | page 27 of 120 ad_secam_en, enable autodetection of secam, address 0x07[6] setting ad_secam_en to 0 (default) disables the autodetection of secam. setting ad_secam_en to 1 enables the detection of secam. ad_n443_en, enable autodetection of ntsc 4.43, address 0x07[5] setting ad_n443_en to 0 disables the autodetection of ntsc style systems with a 4.43 mhz color subcarrier. setting ad_n443_en to 1 (default) enables the detection of ntsc style systems with a 4.43 mhz color subcarrier. ad_p60_en, enable autodetection of pal 60, address 0x07[4] setting ad_p60_en to 0 disables the autodetection of pal systems with a 60 hz field rate. setting ad_p60_en to 1 (default) enables the detection of pal systems with a 60 hz field rate. ad_paln_en, enable autodetection of pal n, address 0x07[3] setting ad_paln_en to 0 (default) disables the detection of the pal n standard. setting ad_paln_en to 1 enables the detection of the pal n standard. ad_palm_en, enable autodetection of pal m, address 0x07[2] setting ad_palm_en to 0 (default) disables the autodetection of pal m. setting ad_palm_en to 1 enables the detection of pal m. ad_ntsc_en, enable autodetection of ntsc, address 0x07[1] setting ad_ntsc_en to 0 (default) disables the detection of standard ntsc. setting ad_ntsc_en to 1 enables the detection of standard ntsc. ad_pal_en, enable autodetection of pal b/d/i/g/h, address 0x07[0] setting ad_pal_en to 0 (default) disables the detection of standard pal. setting ad_pal_en to 1 enables the detection of standard pal. sfl_inv, subcarrier fr equency lock inversion this bit controls the behavior of the pal switch bit in the sfl (genlock telegram) data stream. it was implemented to solve some compatibility issues with video encoders. it solves two problems. first, the pal switch bit is only meaningful in pal. some encoders (including analog devices encoders) also look at the state of this bit in ntsc. second, there was a design change in analog devices encoders from adv717x to adv719x. the older versions used the sfl (genlock telegram) bit directly, whereas the newer ones invert the bit prior to using it. the reason for this is that the inversion compensated for the one line delay of an sfl (genlock telegram) transmission. as a result, for the adv717x and adv73xx encoders, the pal switch bit in the sfl (genlock telegram) must be 0 for ntsc to work. for the adv7194 video encoder, the pal switch bit in the sfl must be 1 to work in ntsc. if the state of the pal switch bit is wrong, a 180 phase shift occurs. in a decoder/encoder back-to-back system in which sfl is used, this bit must be set up properly for the specific encoder used. sfl_inv, subcarrier frequency lock inversion, address 0x41[6] setting sfl_inv to 0 (default) makes the part sfl compatible with the adv717x and adv73xx video encoders. setting sfl_inv to 1 makes the part sfl compatible with the adv7194 video encoder. lock related controls lock information is presented to the user through bits[1:0] of the status 1 register (see the status 1[7:0], address 0x10[7:0] section). figure 19 outlines the signal flow and the controls available to influence the way the lock status information is generated. 1 0 time_win free_run status 1[0] select the r a w lock signal srls filter the raw lock signal cil[2:0], col[2:0] take f sc lock into account fscle status 1[1] f sc lock 1 0 counter into lock counter out of lock memory 05700-016 figure 19. lock related signal path
adv7180 data sheet rev. g | page 28 of 120 srls, select raw lock signal, address 0x51[6] using the srls bit, the user can choose between two sources for determining the lock st atus (per bits[1:0] in the status 1 r egister). see figure 19 . ? the time_win signal is based on a line - to - line evaluation of the horizontal synchronization pulse of the incoming video. it reacts quite quickly. ? the free_run signal evaluates the properties of the incoming video over several fields, taking vertical synchronization information into account. setting srls to 0 (default) selects the free_run signal. setting srls to 1 selects the time_win signal. fscle, f sc lock enable, address 0x51[7] the fscle bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via bits[1:0] in t he s tatus 1 r egister. this bit must be s et to 0 when operating the adv7180 in yprpb component mode to generate a reliable hlock status bit. when fscle is set to 0 (default), only the overall lock status is dependent on horizontal sync lock. when fscle is set to 1, the overall lock status is dep endent on horizontal sync lock and f sc lock. cil[2:0], count into lock, address 0x51[2:0] cil[2:0] determines the number of consecutive lines for which the lock condition must be true before the system switches into the locked state and reports this via st atus 1[1:0]. the bit counts the value in lines of video. table 25 . cil function cil[2:0] number of video lines 000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100,000 col[2:0], count out of lock, address 0 x51[5:3] col[2:0] determines the number of consecutive lines for which the out - of - lock condition must be true before the system switches into the unlocked state and reports this via status 1[1:0]. it counts the value in lines of video. table 26 . col function col[2:0] number of video lines 000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100,000 color controls these registers allow the user to control picture appearance, including control of the active data i n the event of video being lost. these controls are independent of any other controls. for instance, brightness control is independent of picture clamping , although both controls affect the dc level of the signal. con[7:0], contrast adjust, address 0x08[7:0] this register allows the user to control contrast adjustment of the picture. table 27 . con function con[7:0] description 0x80 (default) gain on luma channel = 1 0x00 gain on luma channel = 0 0xff gain on luma channel = 2 sd_ sat_cb[7:0], sd saturation cb channel, address 0xe3[7:0] this register allows the user to control the gain of the cb channel only, which in turn adjusts the saturation of the picture. table 28 . sd_sat_cb function sd_sat_cb[7:0] de scription 0x80 (default) gain on cb channel = 0 db 0x00 gain on cb channel = ?42 db 0xff gain on cb channel = +6 db sd_sat_cr[7:0], sd saturation cr channel, address 0xe4[7:0] this register allows the user to control the gain of the cr channel only, w hich in turn adjusts the saturation of the picture. table 29 . sd_sat_cr function sd_sat_cr[7:0] description 0x80 (default) gain on cr channel = 0 db 0x00 gain on cr channel = ?42 db 0xff gain on cr channel = +6 db
data sheet adv7180 rev. g | page 29 of 120 sd_off_cb[7:0 ], sd offset cb channel, address 0xe1[7:0] this register allows the user to select an offset for the cb channel only and to adjust the hue of the picture. there is a functional overlap with the hue[7:0] register. table 30 . sd_off_c b function sd_off_cb[7:0] description 0x80 (default) 0 mv offset applied to the cb channel 0x00 ?312 mv offset applied to the cb channel 0xff +312 mv offset applied to the cb channel sd_off_cr[7:0], sd offset cr channel, address 0xe2[7:0] this register allows the user to select an offset for the cr channel only and to adjust the hue of the picture. there is a functional overlap with the hue[7:0] register. table 31 . sd_off_cr function sd_off_cr[7:0] description 0x80 (default) 0 mv offset applied to the cr channel 0x00 ?312 mv offset applied to the cr channel 0xff +312 mv of fset applied to the cr channel bri[7:0], brightness adjust, address 0x0a[7:0] this register controls the brightness of the video signal. it allows the user to adjust the brightness of the picture. table 32 . bri function bri[7:0] de scription 0x00 (default) offset of the luma channel = 0 ire 0x7f offset of the luma channel = +30 ire 0x80 o ffset of the luma channel = ?30 ire hue[7:0], hue adjust, address 0x0b[7:0] this register contains the value for the color hue adjustment. it allows the user to adjust the hue of the picture. hue[7:0] has a range of 90, with 0x00 equivalent to an adjust ment of 0. the resolution of hue[7:0] is 1 bit = 0.7. the hue adjustment value is fed into the am color demodulation block. therefore, it applies only to video signals that contain chroma information in the form of an am - modulated carrier (cvbs or y/c in pal or ntsc). it does not affect secam and does not work on component video inputs (yprpb). table 33 . hue function hue[7:0] description (adjust hue of the picture) 0x00 (default) phase of the chroma signal = 0 0x7f phase of the chroma signal = ?90 0x80 phase of the chroma signal = +90 def_y[5:0], default value y, address 0x0c[7:2] when the adv7180 loses lock on the incoming video signal or when there is no input signal, the def_y[5:0] register allows the user to specify a default luma value to be output. this value is used under the following conditions: ? if the def_val_auto_en bit is set to high and the adv7180 has lost lock to the input video signal. t his is the intended mode of operation (automatic mode). ? the def_val_ en bit is set, regardless of the lock status of the video decoder. this is a forced mode that may be useful during configuration. the def_y[5:0] values define the six msbs of the output video. the remaining lsbs are padded with 0s. for example, in 8 - bit mo de, the output is y[7:0] = {def_y[5:0], 0, 0}. for def_y[5:0], 0x0d (blue) is the default value for y. register 0x0c has a default value of 0x36. def_c[7:0], default value c, address 0x0d[7:0] the def_c[7:0] register complements the def_y[5:0] value. it defines the four msbs of cr and cb values to be output if ? the def_val_auto_en bit is set to high and the adv7180 c annot lock to the input video (automatic mode). ? def_val_en bit is set to high (forced output). the data that is finally output from the adv718 0 for the chroma side is cr[3 :0] = {de f_c[7:4], 0, 0, 0, 0}, and cb[3 :0] = {def_c[3:0], 0, 0, 0, 0}. for def_c[7:0], 0x7c (blue) is the default value for cr and cb. def_val_en, default value enable, address 0x0c[0] this bit forces the use of the default values for y, cr, and cb. see the descriptions in the def_y[5:0], default value y, address 0x0c[7:2] and def_c[7:0], default value c, address 0x0d[7:0] sections for add itional information. in this mode, the decoder also outputs a stable 27 mhz clock, hs, and vs. setting def_val_en to 0 (default) outputs a colored screen determined by user - programmable y, cr, and cb values when the decoder free - runs. free - run mode is turn ed on and off by the def_val_auto_en bit. setting def_val_en to 1 forces a colored screen output determined by user - programmable y, cr, and cb values. this overrides picture data even if the decoder is locked.
adv7180 data sheet rev. g | page 30 of 120 def_val_auto_en, default value automatic enable, address 0x0c[1] this bit enables the automatic use of the default values for y, cr, and cb when the adv7180 cannot lock to the video signal. setting def_val_auto_en to 0 disables free-run mode. if the decoder is unlocked, it outputs noise. setting def_val_en to 1 (default) enables free-run mode, and a colored screen set by user-programmable y, cr, and cb values is displayed when the decoder loses lock. clamp operation the input video is ac-coupled into the adv7180. therefore, its dc value needs to be restored. this process is referred to as clamping the video. this section explains the general process of clamping on the adv7180 and shows the different ways in which a user can configure its behavior. the adv7180 uses a combination of current sources and a digital processing block for clamping, as shown in figure 20. the analog processing channel shown is replicated three times inside the ic. while only one single channel is needed for a cvbs signal, two independent channels are needed for y/c (svhs) type signals, and three independent channels are needed to allow component signals (yprpb) to be processed. the clamping can be divided into two sections: ? clamping before the adc (analog domain): current sources. ? clamping after the adc (digital domain): digital processing block. the adc can digitize an input signal only if it resides within the adc 1.0 v input voltage range. an input signal with a dc level that is too large or too small is clipped at the top or bottom of the adc range. the primary task of the analog clamping circuits is to ensure that the video signal stays within the valid adc input window so that the analog-to-digital conversion can take place. it is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits within the adc range. after digitization, the digital fine clamp block corrects for any remaining variations in dc level. because the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. further- more, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must, therefore, be prohibited. the clamping scheme has to complete two tasks. it must acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. to acquire an unknown video signal quickly, the large current clamps should be activated. it is assumed that the amplitude of the video signal at this point is of a nominal value. control of the coarse and fine current clamp parameters is performed automatically by the decoder. standard definition video signals may have excessive noise on them. in particular, cvbs signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mv). a voltage clamp is unsuitable for this type of video signal. instead, the adv7180 employs a set of four current sources that can cause coarse (>0.5 ma) and fine (<0.1 ma) currents to flow into and away from the high impedance node that carries the video signal (see figure 20). the following sections describe the i 2 c signals that can be used to influence the behavior of the clamping block. cclen, current clamp enable, address 0x14[4] the current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. this may be useful if the incoming analog video signal is clamped externally. when cclen is 0, the current sources are switched off. when cclen is 1 (default), the current sources are enabled. co ar se cur r ent sources fine cur r ent sources data pre- processor (dpp) adc video processor with digital fine clamp clamp control analog video input 05700-017 figure 20. clamping overview
data sheet adv7180 rev. g | page 31 of 120 dct[1:0], digital clamp timing, address 0x15[6:5] the clamp timing register determines the time constant of the digital fine clamp circuitry. it is important to note that the digital fine clamp reacts quickly becaus e it immediately corrects any residual dc level error for the active line. the time constant from the digital fine clamp must be much quicker than the one from the analog blocks. by default, the time constant of the digital fine clamp is adjusted dynamical ly to suit the currently connected input signal. table 34 . dct function dct[1:0] description 00 (default) slow (tc = 1 sec) 01 medium (tc = 0.5 sec) 10 fast (tc = 0.1 sec) 11 determined by adv7180, depending on the input video parameters dcfe, digital clamp freeze enable, address 0x15[4] this register bit allows the user to freeze the digital clamp loop at any time. it is intended for users who would like to do their own clamping. users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the dcfe bit. when dcfe is 0 (default), the digital clamp is operational. when dcfe is 1, the digital clamp loop is frozen. luma filter da ta from the digital fine clamp block is processed by the three sets of filters that follow. note that the data format at this point is cvbs for cvbs input or luma only for y/c and yprpb input formats. ? luma antialias filter (yaa). the adv7180 receives video at a rate of 2 8.6363 mhz. ( in the case of 4 oversampled video, the adc samples at 57.27 mhz, and the first decimation is performed inside the dpp filters. therefore, the data ra te into the adv7180 is always 28.6363 mhz.) the itu - r bt.601 recommends a sam pling frequency of 13.5 mhz. the luma antialias filter decimates the oversampled video using a high quality linear phase, low - pass filter that preserves the luma signal while at the same time attenuating out - of - band components. the luma antialias filter (y aa) has a fixed response. ? luma shaping filters (ysh). the shaping filter block is a programmable low - pass filter with a wide variety of responses. it can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example) . for some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. a follow - on video compression stage may work more efficiently if the video is low - pass filtered. the adv7180 has two resp onses for the shaping filter: one that is used for good quality composite, component, and svhs type sources, and a second for nonstandard cvbs signals. the ysh filter responses also include a set of notches for pal and ntsc. however, using the comb filters for y/c separation is recommended. ? digital resampling filter. this block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video. fundamentally, the resampler is a set of low - pass filters. the actual resp onse is chosen by the system with no requirement for user intervention. figure 22 through figure 25 show the overall response of all filters together. unless otherwi se noted, the filters are set into a typical wideband mode. y shaping filter for input signals in cvbs format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. y/c separation must aim for best possib le crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. high quality y/c separation can be achieved by using the internal comb filters of the adv7180. comb filtering, however, relies on the frequency r elationship of the luma component (multiples of the video line rate) and the color subcarrier (f sc ). for good quality cvbs signals, this relationship is known; the comb filter algorithms can be used to separate luma and chroma with high accuracy. in the c ase of nonstandard video signals, the frequency relationship may be disturbed , and the comb filters may not be able to remove all crosstalk artifacts in the best fashion without the assistance of the shaping filter block.
adv7180 data sheet rev. g | page 32 of 120 an automatic mode is provided th at allows the adv7180 to evaluate the quality of the incoming video signal and select the filter responses in accordance with the signal quality and video standard. yfsm, wysfmovr, and wysfm allow the user to manually override the automatic decisions in pa rt or in full. the luma shaping fil ter has three control registers. ? ysfm[4:0] allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (depending on video quality and video standard). ? wysfm ovr allows the user to manually override the wysfm decision. ? wysfm[4:0] allows the user to select a different shaping filter mode for good quality composite (cvbs), component (yprpb), and svhs (y/c) input signals. in automatic mode, the system preserves th e maximum possible bandwidth for good cvbs sources (because they can be successfully combed) as well as for luma components of yprpb and y/c sources (because they need not be combed). for poor quality signals, the system selects from a set of proprietary s haping filter responses that complements comb filter operation to reduce visual artifacts. the decisions of the control logic are shown in figure 21. ysfm[4:0], y shaping filter mode, address 0x17[4:0] the y s haping filter mode bits allow the user to select from a wide range of low - pass and notch filters. when switched in automatic mode, the filter selection is based on other register selections, such as detected video standard, as well as properties extracted from the incoming video itself, such as quality and time base stability. the automatic selection always selects the widest possible bandwidth for the video input encountered. the y - shaping filter mode operates as follows: ? if the ysfm settings specify a fi lter (that is, ysfm is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality. ? in automatic selection mode, the notch filters are only used for bad quality video signals. for all other video signals, wideband filters are used. wysfmovr, wideband y shaping filter override, address 0x18[7] setting the wysfmovr bit enables the use of the wysfm[4:0] settings for good quality video signals. for more information on luma shaping filters , see the y shaping filter section and the flowchart shown in figure 21 . when wysfmovr is 0, the shaping filter for good quality video signals is selected automatically. setting wysfmovr to 1 (default) enables manual override via wysfm[4:0]. auto select luma sha ping filter to complement comb set ysfm ysfm i n auto mode? 00000 o r 0000 1 video q ua lity ba d goo d select wide ban d filter as per wysfm[4:0] select automatic wide band filter wysfmovr 1 0 use ysfm selected filter reg ard less o f vide o q ua lity yes no 05700-018 figure 21 . ysfm and wysfm control flowchart
data sheet adv7180 rev. g | page 33 of 120 table 35 . ysfm function ysfm[4:0] description 00000 autom atic selection including a wide notch res ponse (pal/ntsc/secam) 00001 (default) automat ic selection including a narrow notch response (pal/ntsc/secam) 00010 svhs 1 00011 svhs 2 00100 svhs 3 00101 svhs 4 00110 svhs 5 00111 svhs 6 01000 svhs 7 01001 svhs 8 01010 svhs 9 01011 svhs 10 01100 svhs 11 01101 svhs 12 01110 svhs 13 01111 svhs 14 10000 svhs 15 10001 svhs 16 10010 svhs 17 10011 svhs 18 (ccir 601) 10100 pal nn1 10101 pal nn2 10110 pal nn3 10111 pal wn1 11000 pal wn2 11001 ntsc nn1 11010 ntsc nn2 11011 ntsc nn3 11100 ntsc wn1 11101 ntsc wn2 11110 ntsc wn3 11111 reserved wysfm[4:0], wideband y shaping filter mode, address 0x18[4:0] the wysfm[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, cvbs with stable time base, luma component of yprpb, and luma component of y/c. the wysfm bits are active only if the wysfmovr bit i s set to 1. see the general discussion of the shaping filter settings in the y shaping filter se ction. table 36 . wysfm function wysfm[4:0] description 00000 do not use 00001 do not use 00010 svhs 1 00011 svhs 2 00100 svhs 3 00101 svhs 4 00110 svhs 5 00111 svhs 6 01000 svhs 7 01001 svhs 8 01010 svhs 9 01011 svhs 10 01100 svhs 11 01101 svhs 12 01110 svhs 13 01111 svhs 14 10000 svhs 15 10001 svhs 16 10010 svhs 17 10011 (default) svhs 18 (ccir 601) 10100 to 11111 do not use the filter plots in figure 22 show the s vhs 1 (narrowest) to svhs 18 (widest) shaping filter settings. figure 24 shows the pal notch filter responses. the ntsc - compatible notches are shown in figure 25 . 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 0 10 864 2 12 frequency (mhz) combined y antialias, svhs low-pass filters, y resample amplitude (db) 05700-019 figure 22 . y svhs combined responses
adv7180 data sheet rev. g | page 34 of 120 chroma filter data from the digital fine clamp block is processed by the three sets of filters that follow. note that the data format at this point is cvbs for cv bs inputs, chroma only for y /c , or u/v interleaved for yprpb input formats. ? chroma antialias filter (caa). the adv7180 oversamples the cvbs by a factor of 4 and the chroma/yprpb by a factor of 2. a decimating filter (caa) is used to preserve the active video band and to remove any ou t- of - band components. the caa filter has a fixed response. ? chroma shaping filters (csh). the shaping filter block (csh) can be programmed to perform a variety of low - pass responses. it can be used to selectively reduce the bandwidth of the chroma signal f or scaling or compression. ? digital resampling filter. this block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video. fundamentally, the resampler is a set of low - pass filters. the actual response is c hosen by the system without user intervention. figure 26 shows the overall response of all filters together. 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10 864 2 12 frequency (mhz) amplitude (db) combined y an tialias, cc ir mode s ha ping fi lt er, y resample 05700-020 figure 23 . combined y antialias, ccir mode shaping filter 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 0 10 864 2 12 frequency (mhz) combined y an tialias, pal not ch fi lt ers, y resample amplitude (db) 05700-021 figure 24 . combined y antialias, pal notch filters 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 0 10 864 2 12 frequency (mhz) combined y an tialias, ntsc not ch fi lt ers, y resample amplitude (db) 05700-022 figure 25 . combined y antialias filter, ntsc notch filters 0 ?10 ?20 ?30 ?40 ?50 ?60 0 5 432 1 6 frequency (mhz) combined c an tialias, c s ha ping fi lt er, c resampler a ttenu a tion (db) 05700-023 figure 26 . chroma shaping filter responses
data sheet adv7180 rev. g | page 35 of 120 csfm[2:0], c shaping filter mode, address 0x17[7:5] the c shaping filter mode bits allow the user to select from a range of low - pass filters for the chrominance signal. when switched in automatic mode, the widest filter is selected based on the video standard/format and user choice (see s etting 000 and setting 001 in table 37). table 37 . csfm function csfm[2:0] description 000 (default) auto selection 1.5 mhz bandwidth 001 auto selection 2.17 mhz bandwidth 010 sh1 011 sh2 100 sh3 101 sh4 110 sh5 111 wideband mode figure 26 shows the responses of sh1 (narrowest) to sh5 (widest) in addition to the wideband mode (shown in red). gain operation the gain control within the adv 7180 is done on a purely digital basis. the input adc supports a 10 - bit range mapped into a 1.0 v analog voltage range. gain correction takes place after the digitization in the form of a digital multiplier. advantages of this architecture over the commonl y used programmable gain amplifier (pga) before the adc include the fact that the gain is now completely independent of supply, temperature, and process variations. as shown in figure 28 , the adv7180 can decode a video signal as long as it fits into the adc window. the components for this are the amplitude of the input signal and the dc level it resides on. the dc level is set by the clamping circuitry (see the clamp op eration section). if the amplitude of the analog video signal is too high, clipping may occur, resulting in visual artifacts. the analog input range of the adc, together with the clamp level, determines the maximum supported amplitude of the video signal. figure 27 shows a typical voltage divider network that is required to keep the input video signal within the allowed range of the adc, 0 v to 1 v. this circuit should be placed before all analog inputs to the adv7180. 39 36 100 nf ana l og video input ain_of_ ad v7180 05700-024 figure 27 . input voltage divider network the minimum supported amplitude of the input video is determined by the ability of the adv7180 to retrieve horizontal and vertical timing and to lock to the color burst, if prese nt. there are separate gain control units for luma and chroma data. both can operate independently of each other. the chroma unit, however, can also take its gain value from the luma path. the possible agc modes are shown in table 38. table 38 . agc modes input video type luma gain chroma gain any manual gain luma manual gain chroma cvbs dependent on horizontal sync depth dependent on color - burst amplitude taken from luma path peak whit e dependent on color - burst amplitude taken from luma path y/c dependent on horizontal sync depth dependent on color - burst amplitude taken from luma path peak white dependent on color - burst amplitude yprpb dependent on horizontal sync depth taken from l uma path it is possible to freeze the automatic gain control loops. this causes the loops to stop updating and the agc determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed. th e currently active gain from any of the modes can be read back. refer to the description of the dual - function manual gain registers, lg[11:0] luma gain and cg[11:0] chroma gain, in the luma gain and chroma gain sections. ana l og voltage ran ge supported by adc (1v ran ge for ad v7180 ) data pre- processor (dpp) ad c video processor (gain select io n o nly) maximum voltage minimum voltage clamp level gain control 05700-025 figure 28 . gain control overview
adv7180 data sheet rev. g | page 36 of 120 luma gain lagc[2:0], luma automatic gain control, address 0x2c[6:4] the luma automatic gain control mode bits select the operating mode fo r the gain control in the luma path. there are internal parameters (analog devices proprietary algorithms) to customize the peak white gain control. contact local analog devices field applications engineers or local analog devices distributor for more info rmation. table 39 . lagc function lagc[2:0] description 000 manual fixed gain (use lmg[11:0]) 001 agc (blank level to sync tip), peak white algorithm off 010 (default) agc (blank level to sync tip), peak white algorithm on 011 r eserved 100 reserved 101 reserved 110 reserved 111 freeze gain lagt[1:0], luma automatic gain timing, address 0x2f[7:6] the luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control. t his register only has an effect if the l agc[2:0] register is set to 001 or 010 (automatic gain control modes). if peak white agc is enabled and active (see the status 1[7:0], address 0x10[7:0] section), the a ctual gain update speed is dictated by the peak white agc loop and, as a result, the lagt settings have no effect. as soon as the part leaves peak white agc, lagt becomes relevant again. the update speed for the peak white algorithm can be customized by th e use of internal parameters. contact analog devices local field engineers for more information. table 40 . lagt function lagt[1:0] description 00 slow (tc = 2 sec) 01 medium (tc = 1 sec) 10 fast (tc = 0.2 sec) 11 (default) adapt ive lg[11:0], luma gain, address 0x2f[3:0], address 0x30[7:0] lmg[11:0], luma manual gain, address 0x2f[3:0], address 0x30[7:0] luma gain[11:0] is a dual - function register. if all of these registers are written to, a desired manual luma gain can be prog rammed. this gain becomes active if the lagc[2:0] mode is switched to manual fixed gain. equation 1 shows how to calculate a desired gain. if read back, this register returns the current gain value. depending on the setting in the lagc[2:0] bits, the value is one of the following: ? luma manual gain value (lagc[2:0] set to luma manual gain mode) ? luma automatic gain value (lagc[2:0] set to any of the automatic modes) table 41 . lg/lmg function lg[11:0]/lmg[11:0] read/write description lmg[11:0] = x write manual gain for luma path lg[11:0] = x read actual used gain rationfacto lumacalibr lmg gain luma 0]:[11 = (1) w here lmg[11:0] is a decimal value between 1024 and 4095 . calculation of the luma calibration factor 1. using a video source , set content to a grey field and apply as a standard cvbs signal to the cvbs input of the board. 2. using an oscilloscope , measure the signal at cvbs input to ensure that its sync depth, colour burst , and luma are at the standard levels. 3. connect the output parallel pixel bus of the adv7180 to a backend system that has unity gain and monitor output voltage. 4. measure the luma level correctly from the black level. turn off the luma agc and manually change the value of the luma gain control register, lmg[11:0] , until the output l uma leve l matches the input measured in s tep 2. this value, in decimal, is the lu ma calibration f actor.
data sheet adv7180 rev. g | page 37 of 120 betacam, enable betacam levels, address 0x01[5] if yprpb data is routed through the adv7180, the automatic gain control modes can target different video input levels, as outlined in table 44 . the betacam bit is valid only if the input mode is yprpb (component). the betacam bit sets the target value for agc operation. a review of the following sections is useful: ? the man_mux_en, manual input muxing enable, address 0xc4[7] section for how component video (yprpb) can be routed through the adv7180. ? the video standard selection section to select the various standards, for example, with and without pedestal. the agc algorithms adjust the levels based on the setting of the betacam bit (see table 42). pw_upd, peak white update, address 0x2b[0] the peak white and average video algorithms determine the gain based on measurements taken from the active video. the pw_upd bit determines the rate of gain change. lagc[2:0] must be set to the appropriate mode to enable the peak white or average video mod e in the first place. for more information, see the lagc[2:0], luma automatic gain control, address 0x2c[6:4] s ection. set ting pw_upd to 0 updates the gain once per video line. setting pw_upd to 1 (default) up dates the gain once per field. chroma gain cagc[1:0], chroma automatic gain control, address 0x2c[1:0] the two bits of color automatic gain control mode select the basic mode of operation for automatic gain control in the chroma path. table 42 . betacam function betacam description 0 (default) assuming yprpb is selected as input format: selecting pal with pedestal selects mii . selecting pal without pedestal selects smpte . selecting ntsc with pedestal selects mii . selecting ntsc without pedestal selects smpte . 1 assuming yprpb is selected as input format: selecting pal with pedestal selects betacam . selecting pal without pedestal selects betacam variant . selecting ntsc with pedestal selects betacam . selecting ntsc without pedestal selects betacam variant . table 43 . cagc function cagc[1:0] description 00 manual fixed gain (use cmg[11:0]) 01 l uma gain used for chroma 10 (default) automatic gain (based on color burst) 11 freeze chroma gain table 44 . betacam levels name betacam (mv) betacam variant (mv) smpte (mv) mii (mv) y 0 to +714 (including 7.5% pedestal) 0 to +714 0 to +700 0 to +700 (including 7.5% pedestal) pb and pr ? 467 to +467 ? 505 to +505 ? 350 to +350 ? 324 to +324 sync depth +286 +286 +300 +300
adv7180 data sheet rev. g | page 38 of 120 cagt[1:0], chroma automatic gain timing, address 0x2d[7:6] the chroma automatic gain timing register allows the user to influence the tracking speed of the chroma auto matic gain control. this register has an effect only if the cagc[1:0] register is set to 10 (automatic gain). table 45 . cagt function cagt[1:0] description 00 slow (tc = 2 sec) 01 medium (tc = 1 sec) 10 reserved 11 (default) ada ptive cg[11:0], chroma gain, address 0x2d[3:0], address 0x2e[7:0]; cmg[11:0], chroma manual gain, address 0x2d[3:0], address 0x2e[7:0] chroma gain[11:0] is a dual - function register. if written to, a desired manual chroma gain can be programmed. this gain becomes active if the cagc[1:0] function is switched to manual fixed gain. see equation 2 for calculating a desired gain. if read back, this register returns the current gain value. depending on the setting in the cagc[1:0] bits, this is either: ? the chrom a manual gain value (cagc[1:0] set to chroma manual gain mode). ? the chroma automatic gain value (cagc[1:0] set to any of the automatic modes). table 46 . cg/cmg function cg[11:0]/cmg[11:0] read/write description cmg[11:0] write manu al gain for chroma path cg[11:0] read currently active gain chroma_gain tor brationfac chromacali cmg decimal ]0:11[ ? (2) w here chromacalibration factor is a decimal value between 0 and 4095. calculation of the chroma calibration factor 1. apply a cvbs signal with the c olor bars /smpte b ars test pattern content directly to the measurement equipment. 2. ensure correct termination of 75 ? on the measurement equipment. measure chroma output levels. 3. reconnect the source to the cvbs input of the adv7180 system that has a backend gain of 1. r epeat the measurement of chroma levels. 4. turn off the chroma agc and manually change the chroma gain co ntrol register cmg[11:0] until the chroma level matches that measured directly from the source. this value, in decimal, is the c hroma c alibration f actor. cke, color kill enable, address 0x2b[6] the color kill enable bit allows the optional color kill funct ion to be switched on or off. for qam - based video standards (pal and ntsc) as well as fm - based systems (secam), the threshold for the color kill decision is selectable via the ckillthr[2:0] bits. if color kill is enabled and the color carrier of the incom ing video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). to switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. the color kill option works only for input signals with a modulated chroma part. for component input (yprpb), there is no color kill. setting cke to 0 disables color kill. setting cke to 1 (default) enables color kill. ckillthr[2:0], color kill t hreshold, address 0x3d[6:4] the ckillthr[2:0] bits allow the user to select a threshold for the color kill function. the threshold applies only t o qam - based (ntsc and pal) or fm - modulated (secam) video standards. to enable the color kill function, the cke bit must be set. for setting 000, setting 001, setting 010, and setting 011, chroma demodulation inside the adv7180 may not work satisfactorily for poor input video signals. table 47 . ckillthr function description ckillthr[2:0] secam ntsc, pal 000 no color kill kill at <0.5% 001 kill at <5% kill at <1.5% 010 kill at <7% kill at <2.5% 011 (default) kill at <8% kill at <4% 100 kill at <9.5% kill at <8.5% 101 kill at <15% kill at <16% 110 kill at <32% kill at <32% 111 reserved for analog devices internal use only ; d o not select
data sheet adv7180 rev. g | page 39 of 120 chroma transient improvement (cti) the signal bandwidth allocated for chroma is typically much smaller than that for luminance. in the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. the uneven bandwidth, however, may lead to visual artifacts in sharp color transitions. at the border of two bars of color, both components (luma and chroma) change at the same time (see figure 29). due to the higher bandwidth, the signal transition of the luma component is usually much sharper than that of the chroma component. the color edge is not sharp and can be blurred, in the worst case, over several pixels. luma signal demodulated chroma signal luma signal with a transition, accompanied by a chroma transition original, slow chroma transition prior to cti sharpened chroma transition at the output of cti 05700-026 figure 29. cti luma/chroma transition the chroma transient improvement block examines the input video data. it detects transitions of chroma and can be programmed to create steeper chroma edges in an attempt to artificially restore lost color bandwidth. the cti block, however, operates only on edges above a certain threshold to ensure that noise is not emphasized. care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided. chroma transient improvements are needed primarily for signals that have severe chroma bandwidth limitations. for those types of signals, it is strongly recommended to enable the cti block via cti_en. cti_en, chroma transient improvement enable, address 0x4d[0] setting cti_en to 0 disables the cti block. setting cti_en to 1 (default) enables the cti block. cti_ab_en, chroma transient improvement alpha blend enable, address 0x4d[1] the cti_ab_en bit enables an alpha blend function within the cti block. if set to 1, the alpha blender mixes the transient improved chroma with the original signal. the sharpness of the alpha blending can be configured via the cti_ab[1:0] bits. for the alpha blender to be active, the cti block must be enabled via the cti_en bit. setting cti_ab_en to 0 disables the cti alpha blender. setting cti_ab_en to 1 (default) enables the cti alpha-blend mixing function. cti_ab[1:0], chroma transient improvement alpha blend, address 0x4d[3:2] the cti_ab[1:0] controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one. it thereby controls the visual impact of cti on the output data. for cti_ab[1:0] to become active, the cti block must be enabled via the cti_en bit, and the alpha blender must be switched on via cti_ab_en. sharp blending maximizes the effect of cti on the picture but may also increase the visual impact of small amplitude, high frequency chroma noise. table 48. cti_ab function cti_ab[1:0] description 00 sharpest mixing between sharpened and original chroma signal 01 sharp mixing 10 smooth mixing 11 (default) smoothest alpha blend function cti_c_th[7:0], cti chroma threshold, address 0x4e[7:0] the cti_c_th[7:0] value is an unsigned, 8-bit number specifying how big the amplitude step in a chroma transition must be to be steepened by the cti block. programming a small value into this register causes even smaller edges to be steepened by the cti block. making cti_c_th[7:0] a large value causes the block to improve large transitions only. the default value for cti_c_th[7:0] is 0x08, indicating the threshold for the chroma edges prior to cti.
adv7180 data sheet rev. g | page 40 of 120 digital noise reduct ion (dnr) and luma peaking filter digita l noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal, therefore, improves picture quality. the following are the two dnr blocks in the adv7180: the dnr1 block before the luma peaking filter and the dnr2 block after the luma peaking filter, as shown in figure 30 . luma output dnr 1 luma pe ak ing fi lter dnr 2 luma sig na l 05700-051 figure 30 . dnr and peaking block diagram dnr_en, digital noise reduction enable, address 0x4d[5] the dnr_en bit enables the dnr block or bypasses it. table 49 . dnr_en function setting description 0 bypasses dnr (disable) 1 ( d efault) enables digital noise reduction on the luma data dnr_th[7:0], dnr noise threshold, address 0 x50[7:0] the dnr1 block is positioned before the luma peaking block. the dnr_th[7:0] value is an unsigned, 8 - bit number used to determine the maximum edge that is interpreted as noise and, therefore, blanked from the luma data. programming a large value in to dnr_th[7:0] causes the dnr block to interpret even large transients as noise and remove them. as a result, the effect on the video data is more visible. programming a small value causes only small transients to be seen as noise and to be removed. table 50 . dnr_th[7:0] function setting description 0x08 ( d efault) threshold for maximum luma edges to be interpreted as noise peaking_gain[7:0], luma peaking gain, address 0xfb[7:0] this filter can be manually enabled. the user can se lect to boost or to attenuate the mid region of the y spectrum around 3 mhz. the peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 mhz. the default value on this reg ister passes through the luma data unaltered. a lower value attenuates the signal, and a higher value gains the luma signal. a plot of the filters responses is shown in figure 31. table 51 . peaking_gain[7:0] function setting description 0x40 (default) 0 db response 15 ?20 0 7 05700-052 frequency (mhz) fi l ter response (db) 10 5 0 ?5 ?10 ?15 1 2 3 4 5 6 peak in g g ain using bp filter figure 31 . peaking filter responses dnr_th2[7:0], dnr noise threshold 2, address 0xfc[7:0] the dnr2 block is positioned after the luma peaking bloc k and, therefore, affects the gained luma signal. it operates in the same way as the dnr1 block, but there is an independent threshold control, dnr_th2[7:0], for this block. this value is an unsigned, 8 - bit number used to determine the maximum edge that is interpreted as noise and, therefore, blanked from the luma data. programming a large value into dnr_th2[7:0] causes the dnr block to interpret even large transients as noise and remove them. as a result, the effect on the video data is more visible. programming a small value causes only small transients to be seen as noise and to be removed. table 52 . dnr_th2[7:0] function setting description 0x04 ( d efault) threshold for maximum luma edges to be interpreted as noise
data sheet adv7180 rev. g | page 41 of 120 comb filters the comb filters of the adv7180 have been greatly improved to automatically handle video of all types, standards, and levels of quality. the ntsc and pal configuration registers allow the user to customize the comb filter operation depending on which video standard is detected (by autodetection) or selected (by manual programming). in addition to the bits listed in this section, there are some o ther internal controls (based on analog devices proprietary algorithms); contact local analog devices field engine ers for more information. ntsc comb filter settings these settings are used for ntsc m/j cvbs inputs. nsfsel[1:0], split filter selection ntsc, address 0x19[3:2] the nsfsel[1:0] control selects how much of the overall signal bandwidth is fed to the comb s. a narrow split filter selection results in better performance on diagonal lines but more dot crawl in the final output image. the opposite is true for selecting a wide bandwidth split filter. table 53 . nsfsel function nsfsel[1:0] description 00 (default) narrow 01 medium 10 medium 11 wide ctapsn[1:0], chroma comb taps, ntsc, address 0x38[7:6] table 54 . ctapsn function ctapsn[1:0] description 00 do not use 01 ntsc chroma comb adapts three lines (three taps) to two lines (two taps) 10 (default) ntsc chroma comb adapts five lines (five taps) to three lines (three taps) 11 ntsc chroma comb adapts five lines (five taps) to four lines (four taps) ccmn[2:0], chroma comb mode, ntsc, address 0x38[5:3] table 55 . ccmn function ccmn[2:0] description configuration 000 (default) adaptive comb mode adaptive three - line chroma comb for ctapsn = 01 adaptive four - line chroma comb for ctapsn = 10 adaptive five - line chroma comb fo r ctapsn = 11 100 disable chroma comb 101 fixed chroma comb (top lines of line memory) fixed two - line chroma comb for ctapsn = 01 fixed three - line chroma comb for ctapsn = 10 fixed four - line chroma comb for ctapsn = 11 110 fixed chroma comb (all lines of line memory) fixed three - line chroma comb for ctapsn = 01 fixed four - line chroma comb for ctapsn = 10 fixed five - line chroma comb for ctapsn = 11 111 fixed chroma comb (bottom lines of line memory) fixed two - line chroma comb for ctapsn = 01 fixed three - line chroma comb for ctapsn = 10 fixed four - line chroma comb for ctapsn = 11
adv7180 data sheet rev. g | page 42 of 120 ycmn[2:0], luma comb mode ntsc, address 0x38[2:0] table 56 . ycmn function ycmn[2:0] description configuration 000 (default) ad aptive comb mode adaptive three - line (three taps) luma comb 100 disable luma comb use low - pass/notch filter; see the y shaping filter section 101 fixed luma comb (top lines of line memory) fixed two - line (two taps) luma comb 110 fixed luma comb (all lines of line memory) fixed three - line (three taps) luma comb 111 fixed luma comb (bottom lines of line memory) fixed two - line (two taps) luma comb pal comb filter settings these settings are used for pal b/g/h /i/d, pa l m, pa l combinational n, pal 60, and ntsc 4.43 cvbs inputs. psfsel[1:0], split filter selection, pal, address 0x19[1:0] the psfsel[1:0] control selects how much of the overall signal bandwidth is fed to the combs. a wide split filter selection e liminates dot crawl but shows imperfections on diagonal lines. the opposite is true for selecting a narrow bandwidth split filter . table 57 . psfsel function psfsel[1:0] description 00 narrow 01 (default) medium 10 wide 11 wid est ctapsp[1:0], chroma comb taps pal, address 0x39[7:6] table 58 . ctapsp function ctapsp[1:0] description 00 do not use . 01 pal chroma comb adapts five lines (three taps) to three lines (two taps); cancels cross luma only 10 pal chroma comb adapts five lines (five taps) to three lines (three taps); cancels cross luma and hue error less well 11 (default) pal chroma comb adapts five lines (five taps) to four lines (four taps); cancels cross luma and hue error well ccmp[2:0], chroma comb mode pal, address 0x39[5:3] table 59 . ccmp function ccmp[2:0] description configuration 000 (default) adaptive comb mode adaptive three - line chroma comb for c tapsn = 01 adaptive four - line chroma comb for c tapsn = 10 a daptive five - line chroma comb for c tapsn = 11 100 disable chroma comb 101 fixed chroma comb (top lines of line memory) fixed two - line chroma comb for ctapsn = 01 fixed three - line chroma comb for ctapsn = 10 fixed four - line chroma comb for ctapsn = 11 1 10 fixed chroma comb (all lines of line memory) fixed three - line chroma comb for ctapsn = 01 fixed four - line chroma comb for ctapsn = 10 fixed five - line chroma comb for ctapsn = 11 111 fixed chroma comb (bottom lines of line memory) fixed two - line chroma comb for ctapsn = 01 fixed three - line chroma comb for ctapsn = 10 fixed four - line chroma comb for ctapsn = 11 ycmp[2:0], luma comb mode pal, address 0x39[2:0] table 60 . ycmp function ycmp[2:0] description configuration 000 (de fault) adaptive comb mode adaptive five lines (three taps) luma comb 100 disable luma comb use low - pass/notch filter; see the y shaping filter section 101 fixed luma comb (top lines of line memory) fixed three lines (two taps) luma comb 110 fixed luma comb (all lines of line memory) fixed five lines (three taps) luma comb 111 fixed luma comb (bottom lines of line memory) fixed three lines (two taps) luma comb
data sheet adv7180 rev. g | page 43 of 120 if filter compensati on iffiltsel[2:0], if filter select, address 0xf8[2:0] the iffiltsel[2:0] register allows the user to compensate for saw filter characteristics on a composite input, as would be observed on tuner outputs. figure 32 and figure 33 show if filter compensation for ntsc and pal, respectively. the options for this feature are as follows: ? bypass mode ? ntsc , consists of three filter characteristics ? pa l , consists of three filter characteristics see table 107 for programming details. 6 ?12 2.0 5.0 05700-053 frequency (mhz) amplitude (db) if comp fi lt ers ntsc z oo med ar o und fsc 4 2 0 ?2 ?4 ?6 ?8 ?10 2.5 3.0 3.5 4.0 4.5 figure 32 . ntsc if filter compensation 6 ?8 3.0 6.0 05700-054 frequency (mhz) amplitude (db) if comp filters pal z oo med ar o und fsc 4 2 0 ?2 ?4 ?6 3.5 4.0 4.5 5.0 5.5 figure 33 . pal if filter compensation
adv7180 data sheet rev. g | page 44 of 120 av code insertion an d controls this s ection describes the i 2 c- based controls that affect the following: ? insertion of av codes into the data stream ? data blanking during the vertical blank interval (vbi) ? the range of data values permitted in the output data stream ? the relative delay of luma vs. chroma signals some of the decoded vbi data is inserted during the horizontal blanking interval. see the gemstar data recovery section for more information. bt.656 - 4, itu - r bt.656 - 4 enable, address 0x04[7] betw een revision 3 and revision 4 of the itu - r bt.656 standards, t he itu has changed the toggling position for the v bit within the sav eav codes for ntsc. the itu - r bt.656 - 4 standard bit allows the user to select an output mode that is compliant with either t he previous or new standard. for further information, visit the international telecommunication union website. note that the standard change only affects ntsc and has no bearing on pal. when itu - r bt.656 - 4 is 0 (default), the itu - r bt.656 - 3 specification i s used. the v bit goes low at eav of line 10 and line 273. when itu - r bt.656 - 4 is 1, the itu - r bt.656 - 4 specification is used. the v bit goes low at eav of line 20 and line 283. sd_dup_av, duplicate av codes, address 0x03[0] depending on the output interface width, it may be necessary to duplicate the av codes from the luma path into the chroma path. in an 8 - bit wide output interface (cb/y/cr/y interleaved data), the av codes are defined as ff/00/00/av, with av being the transmitted word that contains inf ormation about h/v/f. in this output interface mode, the following assignment takes place: cb = ff, y = 00, cr = 00, and y = av. in a 16 - bit output interface (64 - lead lqfp only), where y and cr/cb are delivered via separate data buses, the av code is spr ead over the whole 16 bits. the sd_dup_av bit allows the user to replicate the av codes on both buses; therefore, the full av sequence can be found on the y bus as well as on the cr/cb bus (see figure 34 ). when sd_dup_av is 0 (default), the av codes are in single fashion (to suit 8 - bit interleaved data output). when sd_dup_av is 1, the av codes are duplicated (for 16- bit interfaces). vbi_en, vertical blanking interval data enable, address 0x03[7] the vbi enabl e bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering. all data for line 1 to line 21 is passed through and available at the output port. the adv7180 does not bla nk the luma data and automatically switches all filters along the luma data path into their widest bandwidth. for active video, the filter settings for ysh and ypk are restored. s ee the bl_c_vbi, blank chrom a during vbi, address 0x04[2] section for information on the chroma path. when vbi_en is 0 (default), all video lines are filtered/scaled. when vbi_en is 1, only the active video region is filtered/scaled. y data bu s 00 av y ff 00 00 av y ff cr/cb data bu s 00 00 av cb ff 00 cb av code sect io n av code sect io n ff 00 00 av cb av code sect io n cb/y/cr/y interleaved 8-bit i nterf ac e 16 -bit i nterf ac e 16 -bit i nterf ac e sd_ du p_av = 1 sd_ du p_av = 0 05700-027 figure 34 . av co de duplication control (64 - lead lqfp only)
data sheet adv7180 rev. g | page 45 of 120 bl_c_vbi, blank chroma during vbi, address 0x04[2] setting bl_c_vbi high blanks the cr and cb values of all vbi lines. this is done so any data that may arrive during vbi is not decoded as color and is output th rough cr and cb. as a result, it is possible to send vbi lines into the decoder and then output them through an encoder again, undistorted. without this blanking, any color that is incorrectly decoded would be encoded by the video encoder, thus distorting the vbi lines. setting bl_c_vbi to 0 decodes and outputs color during vbi. setting bl_c_vbi to 1 (default) blanks cr and cb values during vbi. r ange , range selection, address 0x04[0] av codes (as per itu - r bt.656, formerly known as ccir - 656) consist of a f ixed header made up of 0xff and 0x00 values. these two values are reserved and , therefore , are not to be used for active video. additionally, the itu specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 and 240 for chroma. the range bit allows the user to limit the range of values output by the adv7180 to the recommended value range. the adv7180 does not scale the data to fit within the smaller range. any value outside of the range is ignored. in any case, it ensures that the reserved values of 255d (0xff) and 00d (0x00) are not presented on the output pins unless they are part of an av code header. table 61 . range function r ange description 0 16 y 235, 16 c/p 240 1 (default) 1 y 254, 1 c/p 254 auto_pdc_en, automatic programmed delay control, address 0x27[6] enabling auto_pdc_en activates a function within the adv7180 that automatically programs the lta[1:0] and cta[2:0 ] registers to have the chroma and luma data match delays for all modes of operation. if auto_pdc__en is set, the lta[1:0] and cta[2:0] manual registers are not used. if the automatic mode is disabled (by setting the auto_pdc_en bit to 0), the values programmed into the lta[1:0] and cta[2:0] registers become active. when auto_pdc_en is 0, the adv7180 uses the lta[1:0] and cta[2:0] values for delaying luma and chroma samples. see the lta[1:0], luma timing adjust, address 0x27[1:0] section and the cta[2:0], chroma timing adjust, address 0x27[5:3] section. when auto_pdc_en is 1 (default), the adv7180 automatically determines the lta and cta values to have luma and chroma align ed at the output. lta[1:0], luma timing adjust, address 0x27[1:0] the luma timing adjust register allows the user to specify a timing difference between chroma and luma samples. there is a functionality overlap with the cta[2:0] register. for manual programming, use the following defaults: ? cvbs input lta[1:0] = 00 ? y/c input lta[1:0] = 01 ? yprpb input lta[1:0] = 01 table 62 . lta function lta [ 1 : 0 ] description 00 (default) no delay 01 luma 1 clock (37 ns) late 10 luma 2 clock (74 n s) early 11 luma 1 clock (37 ns) early cta[2:0], chroma timing adjust, address 0x27[5:3] the chroma timing adjust register allows the user to specify a timing difference between chroma and luma samples. this can be used to compensate for external filter group delay differences in the luma vs. chroma path and to allow a different number of pipeline delays while processing the video downstream. review this functionality together with the lta[1:0] register. the chroma can be delayed or advanced only in chrom a pixel steps. one chroma pixel step is equal to two luma pixels. the programmable delay occurs after demodulation, where delay cannot be made by luma pixel steps. for manual programming, use the following defaults: ? cvbs input cta[2:0] = 011 ? y/c input cta[ 2:0] = 101 ? yprpb input cta[2:0] = 110 table 63 . cta function cta[2:0] description 000 not a valid setting 001 chroma + two pixels (early) 010 chroma + one pixel (early) 011 (default) no delay 100 chroma ? one pixel (late) 101 chroma ? two pixels (late) 110 chroma ? three pixels (late) 111 not a valid setting
adv7180 data sheet rev. g | page 46 of 120 synchronization output signals hs configuration the following controls allow the user to configure the behavior of the hs output pin only: ? beginning of hs signal via hsb[10:0] ? end of hs signal via hse[10:0] ? polarity of hs using phs the hs begin (hsb) and hs end (hse) registers allow the user to freely position the hs output (pin) within the video line. the values in hsb[10:0] and hse[10:0] are measured in pixel units from the falling edge of hs. using both values, the user can program both the position and length of the hs output signal. hsb[10:0], hs begin, address 0x34[6:4], address 0x35[7:0] the position of this edge is controlled by placing a binary number into hsb[10:0]. the number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after eav code ff, 00, 00, xy (see figure 35). hsb is set to 00000000010b, which is two llc clock cycles from count [0]. the default value of hsb[10:0] is 0x02, indicating that the hs pulse starts two pixels after the falling edge of hs. hse[10:0], hs end, address 0x34[2:0], address 0x36[7:0] the position of this edge is controlled by placing a binary number into hse[10:0]. the number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after eav code ff, 00, 00, xy (see figure 35). hse is set to 00000000000b, which is 0 llc clock cycles from count [0]. the default value of hse[10:0] is 00, indicating that the hs pulse ends 0 pixels after the falling edge of hs. for example, ? to shift the hs toward active video by 20 llcs, add 20 llcs to both hsb and hse, that is, hsb[10:0] = [00000010110], hse[10:0] = [00000010100]. ? to shift the hs away from active video by 20 llcs, add 1696 llcs to both hsb and hse (for ntsc), that is, hsb[10:0] = [11010100010], hse[10:0] = [11010100000]. therefore, 1696 is derived from the ntsc total number of pixels, 1716. ? to move 20 llcs away from active video, subtract 20 from 1716 and add the result in binary to both hsb[10:0] and hse[10:0]. phs, polarity hs, address 0x37[7] the polarity of the hs pin can be inverted using the phs bit. when phs is 0 (default), hs is active low. when phs is 1, hs is active high. table 64. hs timing parameters (see figure 35) standard characteristic hs begin adjust hsb[10:0] (default) hs end adjust hse[10:0] (default) hs to active video llc clock cycles, c in figure 35 (default) active video samples/ line, d in figure 35 total llc clock cycles, e in figure 35 ntsc 00000000010b 00000000000b 272 720y + 720c = 1440 1716 pal 00000000010b 00000000000b 284 720y + 720c = 1440 1728 e active video llc pixel bus hs cr y ff 00 00 xy 80 10 80 10 80 10 ff 00 00 xy cb y cr y cb y cr 4 llc d hsb[10:0] hse[10:0] c e d sav active video h blank eav 05700-028 figure 35. hs timing
data sheet adv7180 rev. g | page 47 of 120 vs and field configuration the following controls allow the user to configure the behavior of the vs and field output pins, as well as the generation of embedded av codes. the 64- lead lqfp has separate vs and field pins. the 48 -lead lqfp , 40 -lead lfcsp , and 32 -l ead lfcsp do not have separate vs and field pins but can output either vs or field on pin 45 (48 -lead lqfp ), pin 37 (40 -lead lfcsp ), or pin 31 (32 -l ead lfcsp ), which is the vs/field pin. sqpe, square pixel mode, address 0x01[2] the sqpe bit allows the user to select the square pixel mode. this mode is not suitable for poor time - based video sources. this mode is recommended for professional applications only and should no t be used with vcr or tuner sources. setting sqpe to 1 enables square pixel mode. the llc for ntsc is 24.5454 mhz and 29.5 mhz for pal. the c rystal frequency does not change. vs/field, address 0x58[0] this feature is used for the 48 -lead lqfp , 40- lead lfcs p, and 32 -l ead lfcsp only. the polarity of this bit determines what signal appears on the vs/field pin. when this bit is set to 0 (default), the field signal is output. when this bit is set to 1, the vsync signal is output. the 64 - lead lqfp has dedicated field and vsync pins. adv encoder - compatible signals via the n e wav m o d e register follow: ? pvs, pf ? hvstim ? vsbho, vsbhe ? vseho, vsehe for ntsc control, ? nvbegdelo, nvbegdele, nvbegsign, nvbeg[4:0] ? nvenddelo, nvenddele, nvendsign, nvend[4:0] ? nftogdelo, nftogde le, nftogsign, nftog[4:0] for pal control, ? pvbegdelo, pvbegdele, pvbegsign, pvbeg[4:0] ? pvenddelo, pvenddele, pvendsign, pvend[4:0] ? pftogdelo, pftogdele, pftogsign, pftog[4:0] newavmode, new av mode, address 0x31[4] when newavmode is 0, eav/sav codes are ge nerated to suit analog devices encoders. no adjustments are possible. setting newavmode to 1 (default) enables the manual position of the vsync, field, and av codes using register 0x32 to register 0x33 and register 0xe5 to register 0xea. default register s ettings are ccir656 compliant; see figure 36 for ntsc and figure 41 for pal. for recommended manual user settings, see tabl e 65 and figure 37 for ntsc and table 66 and figure 42 for pa l . hvstim, horizontal vs timing, address 0x31[3] the hvs tim bit allows the user to select where the vs signal is a sserted within a line of video. some interface circuitry may require vs to go low while hs is low. when hvstim is 0 (default), the start of the line is relative to hse. when hvstim is 1, the start o f the line is relative to hsb. vsbho, vs begin horizontal position odd, address 0x32[7] the vsbho and vsbhe bits select the position within a line at which the vs pin (not the bit in the av code) becomes active. some follow - on chips require the vs pin to c hange state only when hs is high or low. when vsbho is 0 (default), the vs pin goes high in the middle of a line of video (odd field). when vsbho is 1, the vs pin changes state at the start of a line (odd field). vsbhe, vs begin horizontal position even, address 0x32[6] the vsbho and vsbhe bits select the position within a line at which the vs pin (not the bit in the av code) becomes active. some follow - on chips require the vs pin to only change state when hs is high or low. when vsbhe is 0 (default), the vs pin goes high in the middle of a line of video (even field). when vsbhe is 1, the vs pin changes state at the start of a line (even field). vseho, vs end horizontal position odd, address 0x33[7] the vseho and vsehe bits select the position within a lin e at which the vs pin (not the bit in the av code) becomes active. some follow - on chips require the vs pin to change state only when hs is high or low. when vseho is 0 (default), the vs pin goes low (inactive) in the middle of a line of video (odd field). when vseho is 1, the vs pin changes state at the start of a line (odd field). vsehe, vs end horizontal position even, address 0x33[6] the vseho and vsehe bits select the position within a line at which the vs pin (not the bit in the av code) becomes activ e. some follow - on chips require the vs pin to change state only when hs is high or low. when vsehe is 0 (default), the vs pin goes low (inactive) in the middle of a line of video (even field). when vsehe is 1, the vs pin changes state at the start of a li ne (even field). pvs, polarity vs, address 0x37[5] the polarity of the vs pin can be inverted using the pvs bit. when pvs is 0 (default), vs is active high. when pvs is 1, vs is active low.
adv7180 data sheet rev. g | page 48 of 120 pf, polarity field, address 0x37[3] the polarity of the field pin for the 64-lead lqfp part can be inverted using the pf bit. the field pin can be inverted using the pf bit. when pf is 0 (default), field is active high. when pf is 1, field is active low. table 65. user settings for ntsc (see figure 37) register register name write 0x31 vs/field control 1 0x1a 0x32 vs/field control 2 0x81 0x33 vs/field control 3 0x84 0x34 hs position control 1 0x00 0x35 hs position control 2 0x00 0x36 hs position control 3 0x7d 0x37 polarity 0xa1 0xe5 ntsv v bit begin 0x41 0xe6 ntsc v bit end 0x84 0xe7 ntsc f bit toggle 0x06 output video field 1 field 2 h v f output video h v f 525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22 nvbeg[4:0] = 0x05 nvbeg[4:0] = 0x05 nvend[4:0] = 0x04 nvend[4:0] = 0x04 nftog[4:0] = 0x03 nftog[4:0] = 0x03 1 bt.656-4 reg 0x04, bit 7 = 1 1 bt.656-4 reg 0x04, bit 7 = 1 1 applies if newavmode = 0: must be manually shifted if newavmode = 1. 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285 05700-029 figure 36. ntsc default, itu-r bt.656 (the pola rity of h, v, and f is embedded in the data) nvbeg[4:0] = 0x01 nvend[4:0] = 0x04 field 1 output video field output hs output nftog[4:0] = 0x06 vs output 52512345678 91011121314152122 field 2 output video field output hs output vs output 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285 nvbeg[4:0] = 0x01 nvend[4:0] = 0x04 nftog[4:0] = 0x06 05700-030 figure 37. ntsc typical vsync/field positions using the register writes in table 65
data sheet adv7180 rev. g | page 49 of 120 adv anc e be gi n o f vsync by nvbeg[4:0] delay be gi n o f vsync by nvbeg[4:0] vsync be gi n nvbegs ig n o dd field? 0 1 no yes nvbegdelo vsbh o add it io nal delay by 1 line adv anc e by 0.5 line 1 0 1 0 nvbegdele vsbh e add it io nal delay by 1 line adv anc e by 0.5 line 1 0 1 0 not valid for user pr og ra mming 05700-031 figure 38 . ntsc vsync begin nvbegdelo, ntsc vsync begin delay on odd field, address 0xe5 [7] when nvbegdelo is 0 (default), there is no delay. setting nvbegdelo to 1 delays vsync going high on an odd field by a line relative to nvbeg. nvbegdele, ntsc vsync begin delay on even field, address 0xe5[6] when nvbegdele is 0 (default), there is no d elay. setting nvbegdele to 1 delays vsync going high on an even field by a line relative to nvbeg. nvbegsign, ntsc vsync begin si gn, address 0xe5[5] setting nvbegsign to 0 delays the start of vsync. set for user manual programming. setting nvbegsign to 1 (defaul t) advances the start of vsync (n ot recommended for user programming ). nvbeg[4:0], ntsc vsync begin, address 0xe5[4:0] the default value of nvbeg is 00101, indicating the ntsc vsync begin position. for all ntsc/pal vsync timing controls, both t he v bit in the av code and the vsync signal on the vs pin are modified. adv anc e e nd o f vsync by nve nd [4:0] delay e nd o f vsync by nve nd [4:0] vsync end nve nd sig n o dd field? 0 1 no yes nve ndd elo vseho add it io nal delay by 1 line adv anc e by 0.5 line 1 0 1 0 nve ndd ele vsehe add it io nal delay by 1 line adv anc e by 0.5 line 1 0 1 0 not valid for user pr og ra mming 05700-032 figure 39 . ntsc vsync end nvenddelo, ntsc vsync end delay on odd field, address 0xe6[7] when nvenddelo is 0 (default), there is no delay. setting nvenddelo to 1 delays vsync from going low on an odd field by a line relative to nvend. nvenddele, ntsc vsync end delay on even field, address 0xe6[6] when nvenddele is set to 0 (default), there is no delay. setting nvenddele to 1 delays vsync from going low on an even field by a line relative to nvend. nvendsign, ntsc vsync end sign, address 0xe6[5] setting nvendsign to 0 (default) delays the end of vsync. set for user manual programming. setting nvendsign to 1 advances the end of vsync (n ot recommended for user progra mming ).
adv7180 data sheet rev. g | page 50 of 120 nvend[4:0], ntsc vsync end, address 0xe6[4:0] the default value of nvend is 00100, indicating the ntsc vsync end position. for all ntsc/pal vsync timing controls, both the v bit in the av code and the vsync signal on the vs pin are modified. nftogdelo, ntsc field toggle delay on odd field, address 0xe7[7] when nftogdelo is 0 (default), there is no delay. setting nftogdelo to 1 delays the field toggle/transition on an odd field by a line relative to nftog. nftogdele, ntsc field toggle delay on even field, address 0xe7[6] when nftogdele is 0, there is no delay. setting nftogdele to 1 (default) delays the field toggle/ transition on an even field by a line relative to nftog. nftogsign, ntsc field toggle sign, address 0xe7[5] setting nftogsign to 0 delays the field transition. set for user manual programming. setting nftogsign to 1 (default) advances the field transition (not recommended for user programming). nftog[4:0], ntsc field toggle, address 0xe7[4:0] the default value of nftog is 00011, indicating the ntsc field toggle position. for all ntsc/pal field timing controls, both the f bit in the av code and the field signal on the field pin are modified. advance toggle of field by nftog[4:0] delay toggle of field by nftog[4:0] nftogsign odd field? 0 1 no yes nftogdele additional delay by 1line 1 0 nftogdelo additional delay by 1line 1 0 field toggle not valid for user programming 05700-033 figure 40. ntsc field toggle field 1 output video h v f 622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24 pvbeg[4:0] = 0x05 pvend[4:0] = 0x04 pftog[4:0] = 0x03 field 2 output video h v f pvbeg[4:0] = 0x05 pvend[4:0] = 0x04 pftog[4:0] = 0x03 310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337 05700-034 figure 41. pal default, itu-r bt.656 (the polarity of h, v, and f is embedded in the data)
data sheet adv7180 rev. g | page 51 of 120 field 1 622 623 624 625 123 45 678 91011 2324 310 311 312 313 314 315 316 317 318 319 320 321 322 323 336 337 pvbeg[4:0] = 0x01 pvend[4:0] = 0x04 pftog[4:0] = 0x06 field 2 output video field output hs output vs output output video field output hs output vs output pvbeg[4:0] = 0x01 pvend[4:0] = 0x04 pftog[4:0] = 0x06 05700-035 figure 42. pal typical vs/field positions using the register writes shown in table 66 table 66. user settings for pal (see figure 42) register register name write 0x31 vs/field control 1 0x1a 0x32 vs/field control 2 0x81 0x33 vs/field control 3 0x84 0x34 hs position control 1 0x00 0x35 hs position control 2 0x00 0x36 hs position control 3 0x7d 0x37 polarity 0xa1 0xe8 pal v bit begin 0x41 0xe9 pal v bit end 0x84 0xea pal f bit toggle 0x06 pvbegdelo, pal vsync begin delay on odd field, address 0xe8[7] when pvbegdelo is 0 (default), there is no delay. setting pvbegdelo to 1 delays vsync going high on an odd field by a line relative to pvbeg. pvbegdele, pal vsync begin delay on even field, address 0xe8[6] when pvbegdele is 0, there is no delay. setting pvbegdele to 1 (default) delays vsync going high on an even field by a line relative to pvbeg. pvbegsign, pal vsync begin sign, address 0xe8[5] setting pvbegsign to 0 delays the beginning of vsync. set for user manual programming. setting pvbegsign to 1 (default) advances the beginning of vsync (not recommended for user programming). pvbeg[4:0], pal vsync begin, address 0xe8[4:0] the default value of pvbeg is 00101, indicating the pal vsync begin position. for all ntsc/pal vsync timing controls, the v bit in the av code and the vsync signal on the vs pin are modified. advance begin of vsync by pvbeg[4:0] delay begin of vsync by pvbeg[4:0] vsync begin pvbegsign odd field? 0 1 no yes pvbegdelo vsbho additional delay by 1line advance by 0.5 line 1 0 1 0 pvbegdele vsbhe additional delay by 1line advance by 0.5 line 1 0 1 0 not valid for user programming 05700-036 figure 43. pal vsync begin
adv7180 data sheet rev. g | page 52 of 120 adv anc e e nd o f vsync by pve nd [4:0] delay e nd o f vsync by pve nd [4:0] vsync end pvend sig n o dd field? 0 1 no yes pvendd elo vseho add it io nal delay by 1 line adv anc e by 0.5 line 1 0 1 0 pvendd ele vsehe add it io nal delay by 1 line adv anc e by 0.5 line 1 0 1 0 not valid for user pr og ra mming 05700-037 figure 44 . pal vsync end pvenddelo, pal vsync end delay on odd field, address 0xe9[7] when pvenddelo is 0 (default), there is no delay. setti ng pvenddelo to 1 delays vsync going low on an odd field by a line relative to pvend. pvenddele, pal vsync end delay on even field, address 0xe9[6] when pvenddele is 0 (default), there is no delay. setting pvenddele to 1 delays vsync going low on an even field by a line relative to pvend. pvendsign, pal vsync end sign, address 0xe9[5] setting pvendsign to 0 (default) delays the end of vsync (s et for user manual programming ). setting pvendsign to 1 advances the end of vsync (n ot recommended for user program ming ). pvend[4:0], pal vsync end, address 0xe9[4:0] the default value of pvend is 10100, indicating the pal vsync end position. for all ntsc/pal vsync timing controls, both the v bit in the av code and the vsync signal on the vs pin are modified. pftogdel o, pal field toggle delay on odd field, address 0xea[7] when pftogdelo is 0 (default), there is no delay. setting pftogdelo to 1 delays the f toggle/transition on an odd field by a line relative to pftog. pftogdele, pal field toggle delay on even field, ad dress 0xea[6] when pftogdele is 0, there is no delay. setting pftogdele to 1 (default) delays the f toggle/transition on an even field by a line relative to pftog. pftogsign, pal field toggle sign, address 0xea[5] setting pftogsign to 0 delays the field tr ansition. set for user manual programming. setting pftogsign to 1 (default ) advances the field transition (n ot recommended for user programming ). pftog, pal field toggle, address 0xea[4:0] the default value of pftog is 00011, indicating the pal field toggl e position. for all ntsc/pal field timing controls, the f bit in the av code and the field signal on the field pin are modified. adv anc e t ogg le o f field by pft og [4:0] delay t ogg le o f field by pft og [4:0] pft og sig n o dd field? 0 1 no yes pft og dele add it io nal delay by 1 line 1 0 pft og delo add it io nal delay by 1 line 1 0 field t ogg le not valid for user pr og ra mming 05700-038 figure 45 . pal f toggle
data sheet adv7180 rev. g | page 53 of 120 sync processing the adv7180 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. if desired, the blocks can be disabled via the following two i 2 c bits: enhspll and envsproc. enhspll, enable hsync processor, address 0x01[6] the hsync processo r is designed to filter incoming hsyncs that have been corrupted by noise, providing improved performance for video signals with stable time bases but poor snr. setting enhspll to 0 disables the hsync processor. setting enhspll to 1 (default) enables the h sync processor. envsproc, enable vsync processor, address 0x01[3] this block provides extra filtering of the detected vsyncs to improve vertical lock. setting envsproc to 0 disables the vsync processor. setting envsproc to 1 (default) enables the vsync pro cessor. vbi data decode the following are the two vbi data slicers on the adv7180: the vbi data processor (vdp) and the vbi system 2. the vdp can slice both low bandwidth standards and high bandwidth standards such as teletext. vbi system 2 can slice low data rate vbi standards only. the vdp is capable of slicing multiple vbi data standards on sd video. it decodes the vbi data on the incoming cvbs and y/c or yuv data. the decoded results are available as ancillary data in output 656 data stream. for low data rate vbi standards like cc/wss/cgms, users can read the decoded data bytes from the i 2 c registers. the vbi data standards that can be decoded by the vdp are listed in table 67 and table 68 . table 67 . pal feature standard teletext system a, c, or d itu - r bt.653 teletext system b/wst itu - r bt.653 video programming system (vps) etsi en 300 231 v 1.3.1 vertical interval time codes (vitc) not ap plicable wide screen signaling (wss) itu - r bt.1119- 1/ etsi en.300294 closed captioning (ccap) not applicable table 68 . ntsc feature standard teletext system b and d itu - r bt.653 teletext system c/nabts itu - r bt.653/eia - 516 ver tical interval time codes (vitc) not applicable copy generation management system (cgms) eia- j cpr - 1204/iec 61880 gemstar not applicable closed captioning (ccap) eia-608 the vbi data standard that the vdp decodes on a particular line of incoming video has been set by default as described in table 69 . this can be overridden manually and any vbi data can be decoded on any line. the details of manual programming are described in table 70. vdp default configuration the vdp can decode different vbi data standards on a line - to - line basis. the various standards supported by default on different lines of vbi are explained in table 69. vdp manual configuration man_line_pgm, enable manual line programming of vbi standards, address 0x64[7], user sub map the user can configure the vdp to decode different standards on a line - to - line basis through manual line programming. for this, the use r must set the man_line_pgm bit. the user must write into all the line programming registers, vbi_data_px_ny and vbi_data_px (see register 0x64 to register 0x77 in table 108 ). when man_line_pgm to 0 (default) is set , the vdp decodes default standards on lines, as shown in table 69. when man_line_pgm to 1 is set , the vbi standards to be decoded are manually programmed. vbi_data_px_ny[3:0], vbi_data_px[3:0], vbi standard to be decoded on line x for pal, line y fo r ntsc, address 0x64 to address 0x77, user sub map these are related 4 - bit clusters in register 0x64 to register 0x77 of the user sub map. these 4 - bit, line programming registers, vbi_data_px_ny and vbi_data_px , identify the vbi data standard that are decoded on line x in pal mode or on line y in ntsc mode. the different types of vbi standards decoded by vbi_data_px_ny and vbi_data_px are shown in table 70 . note that th e x or y value depends on whether the adv7180 is in pal or ntsc mode.
adv7180 data sheet rev. g | page 54 of 120 table 69 . default standards on lines for pal and ntsc pal 625/50 ntsc 525/60 line no. default vbi data decoded line no. default vbi data decoded line no. default vbi data decoded line no. default vbi data decoded 6 wst 318 vps 23 gemstar_1 286 gemstar_1 7 wst 319 wst 24 gemstar_1 287 gemstar_1 8 wst 320 wst 25 gemstar_1 288 gemstar_1 9 wst 321 wst 10 nabts 272 nabts 10 wst 322 wst 11 nabts 2 73 nabts 11 wst 323 wst 12 nabts 274 nabts 12 wst 324 wst 13 nabts 275 nabts 13 wst 325 wst 14 vitc 276 nabts 14 wst 326 wst 15 nabts 277 vitc 15 wst 327 wst 16 vitc 278 nabts 16 vps 328 wst 17 nabts 279 vitc 17 n/a 329 vps 18 nabts 280 nabts 18 n/ a 332 vitc 19 nabts 281 nabts 19 vitc 333 wst 20 cgms 282 nabts 20 wst 334 wst 21 ccap 283 cgms 21 wst 335 ccap 22 + full odd field nabts 284 ccap 22 ccap 336 wst 285 + full even field nabts 23 wss 337 + full even field wst 24 + full odd field wst table 70 . vbi data standards for manual configuration vbi_data_px_ny 625/50 pal 525/60 ntsc 0000 disable vdp disable vdp 0001 teletext system identified by vdp_ttxt_type teletext system identified by vdp_ttxt_ty pe 0010 vps - etsi en 300 231 v 1.3.1 reserved 0011 vitc vitc 0100 wss itu - r bt.1119 - 1/etsi.en.300294 cgms eia - j cpr - 1204/iec 61880 0101 reserved gemstar_1 0110 reserved gemstar_2 0111 ccap ccap eia -608 1000 to 1111 reserved reserved
data sheet adv7180 rev. g | page 55 of 120 table 71 .vbi data standards to be decoded on line px (pal) or line ny (ntsc) signal name register location dec address hex address vbi_data_p6_n23 vdp_line_00f[7:4] 101 0x65 vbi_data_p7_n24 vdp_line_010[7:4] 102 0x66 vbi_data_p8_n25 vdp_ line_011[7:4] 103 0x67 vbi_data_p9 vdp_line_012[7:4] 104 0x68 vbi_data_p10 vdp_line_013[7:4] 105 0x69 vbi_data_p11 vdp_line_014[7:4] 106 0x6a vbi_data_p12_n10 vdp_line_015[7:4] 107 0x6b vbi_data_p13_n11 vdp_line_016[7:4] 108 0x6c vbi_data_p14_n 12 vdp_line_017[7:4] 109 0x6d vbi_data_p15_n13 vdp_line_018[7:4] 110 0x6e vbi_data_p16_n14 vdp_line_019[7:4] 111 0x6f vbi_data_p17_n15 vdp_line_01a[7:4] 112 0x70 vbi_data_p18_n16 vdp_line_01b[7:4] 113 0x71 vbi_data_p19_n17 vdp_line_01c[7:4] 114 0 x72 vbi_data_p20_n18 vdp_line_01d[7:4] 115 0x73 vbi_data_p21_n19 vdp_line_01e[7:4] 116 0x74 vbi_data_p22_n20 vdp_line_01f[7:4] 117 0x75 vbi_data_p23_n21 vdp_line_020[7:4] 118 0x76 vbi_data_p24_n22 vdp_line_021[7:4] 119 0x77 vbi_data_p318 vdp_li ne_00e[3:0] 100 0x64 vbi_data_p319_n286 vdp_line_00f[3:0] 101 0x65 vbi_data_p320_n287 vdp_line_010[3:0] 102 0x66 vbi_data_p321_n288 vdp_line_011[3:0] 103 0x67 vbi_data_p322 vdp_line_012[3:0] 104 0x68 vbi_data_p323 vdp_line_013[3:0] 105 0x69 vbi _data_p324_n272 vdp_line_014[3:0] 106 0x6a vbi_data_p325_n273 vdp_line_015[3:0] 107 0x6b vbi_data_p326_n274 vdp_line_016[3:0] 108 0x6c vbi_data_p327_n275 vdp_line_017[3:0] 109 0x6d vbi_data_p328_n276 vdp_line_018[3:0] 110 0x6e vbi_data_p329_n277 vdp_line_019[3:0] 111 0x6f vbi_data_p330_n278 vdp_line_01a[3:0] 112 0x70 vbi_data_p331_n279 vdp_line_01b[3:0] 113 0x71 vbi_data_p332_n280 vdp_line_01c[3:0] 114 0x72 vbi_data_p333_n281 vdp_line_01d[3:0] 115 0x73 vbi_data_p334_n282 vdp_line_01e[3: 0] 116 0x74 vbi_data_p335_n283 vdp_line_01f[3:0] 117 0x75 vbi_data_p336_n284 vdp_line_020[3:0] 118 0x76 vbi_data_p337_n285 vdp_line_021[3:0] 119 0x77 note that full field detection (lines other than vbi lines) of any standard can also be enabled by writing into the vbi_data_p24_n22[3:0] and vbi_data_p337_n285[3:0] registers. so, if vbi_data_p24_n22[3:0] is programmed with any teletext standard, then teletext is decoded off for the entire odd field. the corresponding register for the even field is vbi_data_ p337_n285[3:0]. for teletext system identification, vdp assumes that if teletext is present in a video channel, all the teletext lines comply with a single standard system. therefore, the line programming using the vbi_data_px_ny and vbi_data_p x registers identifies whether the data in line is teletext; the actual standard is identified by the vdp_ttxt_type_man bit. to program the vdp_ttxt_type_man bit, the vdp_ttxt_type_man_enable bit must be set to 1.
adv7180 data sheet rev. g | page 56 of 120 vdp_ttxt_type_man_enable, enable manual selection of teletext type, address 0x60[2], user sub map setting vdp_ttxt_type_man_enable to 0 (default), the manual programming of the teletext type is disabled. setting vdp_ttxt_type_man_enable to 1, the manual programming of the teletext type is enabl ed. vdp_ttxt_type_man[1:0], specify the teletext type, address 0x60[1:0], user sub map these bits specify the teletext type to be decoded. these bits are functional only if vdp_ttxt_type_man_enable is set to 1. table 72 . vdp_ttxt_ty pe_man function vdp_ttxt_ type_man[1:0] 625/50 (pal) 525/60 (ntsc) 00 (default) teletext - itu - bt.653 - 625/50 -a reserved 01 teletext - itu - bt.653 - 625/50 - b (wst) teletext - itu - bt.653 - 525/60 -b 10 teletext - itu - bt.653 - 625/50 -c teletext - itu - bt.653 - 525/60 - c or eia5 16 (nabts) 11 teletext - itu - bt.653 - 625/50 -d teletext - itu - bt.653 - 525/60 -d vdp ancillary data output reading the data back via i 2 c may not be feasible for vbi data standards with high data rates (for example, teletext). an alternative is to place the slice d data in a packet in the line blanking of the digital output ccir656 stream. this is available for all standards sliced by the vdp module. when data is sliced on a given line, the corresponding ancillary data packet is placed immediately after the next e av code that occurs at the output (that is, data sliced from multiple lines are not buffered up and then emitted in a burst). note that, due to the vertical delay through the comb filters, the line number on which the packet is placed differs from the line number on which the data was sliced. the user can enable or disable the insertion of vdp results that have been decoded into the 656 ancillary streams by using the adf_enable bit. adf_enable, enable ancillary data output through 656 stream, address 0x62[7 ], user sub map setting adf_enable to 0 (default) disables the insertion of vbi decoded data into the ancillary 656 stream. setting adf_enable to 1 enables the insertion of vbi decoded data into the ancillary 656 stream. the user may select the data ident ification word (did) and the secondary data identification word (sdid) through programming the adf_did[4:0] and adf_sdid[5:0] bits, respectively. adf_did[4:0], user - specified data id word in ancillary data, address 0x62[4:0], user sub map this bit selects the data id word to be inserted into the ancillary data stream with the data decoded by the vdp. the default value of adf_did[4:0] is 10101. adf_sdid[5:0], user - specified secondary data id word in ancillary data, address 0x63[5:0], user sub map these bits select the secondary data id word to be inserted in the ancillary data stream with the data decoded by the vdp. the default value of adf_sdid[5:0] is 101010. duplicate_adf, enable duplication/spreading of ancillary data over y and c buses, address 0x63[7] , user sub map this bit determines whether the ancillary data is duplicated over both y and c buses or if the data packets are spread between the two channels. when duplicate_adf to 0 (default) is set , the ancillary data packet is spread across the y and c data streams. when duplicate_adf to 1 is set , the ancillary data packet is duplicated on the y and c data streams. adf_mode[1:0], determine the ancillary data output mode, address 0x62[6:5], user sub map these bits determine whether the ancillary data ou tput mode is in byte mode or nibble mode. table 73 . adf_mode adf_mode[1:0] description 00 (default) nibble mode 01 byte mode, no code restrictions 10 byte mode, but 0x00 and 0xff prevented ( 0x00 replaced by 0x01, 0xff replaced by 0xfe) 11 reserved
data sheet adv7180 rev. g | page 57 of 120 the ancillary data packet sequence is explained in table 74 and table 75 . the nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is enabled. this format is in compliance with itu - r bt.1364. the following abbreviations are used in table 74 and table 75 : ? ep ev en parity for bit b8 to bit b2. the parity bits ep is set so that an even number of 1s are in bit b8 to bit b2, including the parity bit, d8. ? cs checksum word. the cs word is used to increase confidence of the integrity of the ancillary data packet from the did, sdid, and dc through user data - words (udws). it consists of 10 bits that include the following: a 9 - bit calculated value and b9 as the inverse of b8. the checksum value b8 to b0 is equal to the nine lsbs of the sum of the nine lsbs of the did, sd id, and dc and all udws in the packet. prior to the start of the checksum count cycle, all checksum and carry bits are preset to 0. any carry resulting from the checksum count cycle is ignored. ? ep the msb, b9, is the inverse of ep. this ensures that restricted code 0x00 and code 0xff do not occur. ? line_number [9:0] the line number of the line that immediately precedes the ancillary data packet. the line number is from the numbering system in itu - r bt.470. the line number runs from 1 to 625 in a 625 - line system and from 1 to 263 in a 525 - line system. note that, due to the vertical delay through the comb filters, the line number on which the packet is output differs from the line number on which the vbi data was sliced. ? data count the da ta count specifies the number of udws in the ancillary stream for the standard. the total number of user data - words is four times the data count. padding words can be introduced to make the total number of udws divisible by 4. table 74 . ancillary data in nibble output format byte b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description 0 0 0 0 0 0 0 0 0 0 0 ancillary data preamble 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 ep ep 0 i 2 c_did6_2[4:0] 0 0 did (data i dentification word) 4 ep ep i 2 c_sdid7_2[5:0] 0 0 sdid (secondary data identification word) 5 ep ep 0 dc[4:0] 0 0 data count 6 ep ep padding[1:0] vbi_data_std[3:0] 0 0 id0 (user data - wo rd 1) 7 ep ep 0 line_number[9:5] 0 0 id1 (user data - word 2) 8 ep ep even_field line_number[4:0] 0 0 id2 (user data - word 3) 9 ep ep 0 0 0 0 vdp_ttxt_type[1:0] 0 0 id3 (user data - word 4) 10 ep ep 0 0 vbi_word_1[7:4] 0 0 id4 (user data - word 5) 11 ep ep 0 0 vbi_word_1[3:0] 0 0 id5 (user data - word 6) 12 ep ep 0 0 vbi_word_2[7:4] 0 0 id6 (user data - word 7) 13 ep ep 0 0 vbi_word_2[3:0] 0 0 id7 (user data - word 8) 14 ep ep 0 0 vbi_word_3[7:4] 0 0 id8 (user data - word 9) pad 0x200; these padding words may be present , depending on ancillary data type; user data - word n ? 3 1 0 0 0 0 0 0 0 0 0 n ? 2 1 0 0 0 0 0 0 0 0 0 n ? 1 b8 checksum (cs) 0 0 cs (checksum word)
adv7180 data sheet rev. g | page 58 of 120 table 75 . ancillary data in byte output format 1 byte b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description 0 0 0 0 0 0 0 0 0 0 0 ancillary data preamble 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 ep ep 0 i 2 c_did6_2[4:0] 0 0 did 4 ep ep i 2 c_sdid7_2[5:0] 0 0 sdid 5 ep ep 0 dc[4:0] 0 0 data coun t 6 ep ep padding[1:0] vbi_data_std[3:0] 0 0 id0 (user data - word 1) 7 ep ep 0 line_number[9:5] 0 0 id1 (user data - word 2) 8 ep ep even_field line_number[4:0] 0 0 id2 (user data - word 3) 9 ep ep 0 0 0 0 vdp_ttxt_type[1:0] 0 0 id3 (user data - word 4) 10 vbi_word_1[7:0] 0 0 id4 (user data - word 5) 11 vbi_word_2[7:0] 0 0 id5 (user data - word 6) 12 vbi_word_3[7:0] 0 0 id6 (user data - word 7) 13 vbi_word_4[7:0] 0 0 id7 (user data - word 8) 14 vbi_word_5[7:0] 0 0 id8 (user data - word 9) pad 0x200; these padding words may be present , depending on ancillary data type; user data - word n ? 3 1 0 0 0 0 0 0 0 0 0 n ? 2 1 0 0 0 0 0 0 0 0 0 n ? 1 b8 checksum 0 0 cs (checksum word) 1 this mode does not fully comply with itu - r bt.1364 . structure of vbi words in the ancillary data stream each vbi data standard has been split into a clock - run - in (cri), a framing code (fc), and a number of data bytes (n). the data packet in the ancillary stream includes only the fc and data bytes. table 76 shows the format of vbi_word_x in the ancillary data stream. table 76 . structure of vbi data - words in the ancillary stream ancillary data byte n o. byte type description vbi_word_1 fc0 framing code[23:16] vbi_word_2 fc1 framing code[15:8] vbi_word_3 fc2 framing code[7:0] vbi_word_4 db1 first data byte vbi_wor d_n + 3 dbn last (n th ) data byte vdp framing code the length of the actual framing code depends on the vbi data standard. for uniformity, the length of the framing code reported in the ancillary data stream is always 24 bits. for standards with a smaller framing code length, the extra lsb bits are set to 0. the valid length of the framing code can be decoded from the vbi_data_std bits available in id0 (udw 1). the framing code is always reported in the inverse - transmission order. table 77 shows the framing code and its valid length for vbi data standards supported by vdp. example for teletext (b - wst), the framing code byte is 11100100 (0xe4), with bits shown in the order of transmission. vbi_word_1 = 0x27, vbi_word_2 = 0x00, and vbi_word_3 = 0x00 translated into udws in the ancillary data stream for nibble mode are as follows: udw5[5:2] = 0010 udw6[5:2] = 0111 udw7[5:2] = 0000 (undefined bits set to 0) udw8[5:2] = 0000 (undefined bits set to 0) udw9[5:2] = 0000 (undefined bits set to 0) udw10[5:2] = 0000 (undefined bits set to 0) for byte mode, udw5[9:2] = 0010_0111 udw6[9:2] = 0000_0000 (undefined bits set to 0) udw7[9:2] = 0000_0000 (undefined bits set to 0)
data sheet adv7180 rev. g | page 59 of 120 data bytes vbi_w ord_4 to vbi_word_n + 3 contain the data - words that were decoded by the vdp in the transmission order. the position of bits in bytes is in the inverse transmission order. for example, closed captioning has two user data bytes, as shown in table 82 . the data bytes in the ancillary data stream are as follows: vbi_word_4 = byte 1[7:0] vbi_word_5 = byte 2[7:0] the number of vbi_words for each vbi data standard and the total number of udws in the ancillary data stream is shown in table 78. table 77 . framing code sequence for different vbi standards vbi standard length in bits error - free framing code bits (i n order of transmission) error - free framing code reported by vdp (i n reverse o rder of transmission) ttxt_system_a (pal) 8 11100111 11100111 ttxt_system_b (pal) 8 11100100 00100111 ttxt_system_b (ntsc) 8 11100100 00100111 ttxt_system_c (pal and ntsc) 8 11100111 11100111 ttxt_system_d (pal and ntsc) 8 11100101 10100111 vps (pal) 16 10001010100011001 1001100101010001 vitc (ntsc and pal) 1 0 0 wss (pal) 24 000111100011110000011111 111110000011110001111000 gemstar_1 (ntsc) 3 001 100 gemstar_2 (ntsc) 11 1001_1011_101 101_1101_1001 ccap (ntsc and pal) 3 001 100 cgms (ntsc) 1 0 0 table 78 . total user data - words for different vbi standards 1 vbi standard adf mode framing code udws vbi data - words no. of padding words total udws ttxt_system_a (pal) 00 (nibble mode) 6 74 0 84 01, 10 (byte mode) 3 37 0 44 ttxt_system_b (pal) 00 (nibble mode) 6 84 2 96 01, 10 (byte mode) 3 42 3 52 ttxt_system_b (ntsc) 00 (nibble mode) 6 68 2 80 01, 10 (byte mode) 3 34 3 44 ttxt_system_c (pal and ntsc) 00 (nibble mode) 6 66 0 76 01, 10 (byte mode) 3 33 2 42 ttxt_system_d (pal and ntsc) 00 (nibble mode) 6 68 2 80 01, 10 (byte mode) 3 34 3 44 vps (pal) 00 (nibble mode) 6 26 0 36 01, 10 (byte mode) 3 13 0 20 vitc (ntsc and pal) 00 (nibble mode) 6 18 0 28 01, 10 (byte mode) 3 9 0 16 w ss (pal) 00 (nibble mode) 6 4 2 16 01, 10 (byte mode) 3 2 3 12 gemstar_1 (ntsc) 00 (nibble mode) 6 4 2 16 01, 10 (byte mode) 3 2 3 12 gemstar_2 (ntsc) 00 (nibble mode) 6 8 2 20 01, 10 (byte mode) 3 4 1 12 ccap (ntsc and pal) 00 (nibb le mode) 6 4 2 16 01, 10 (byte mode) 3 2 3 12 cgms (ntsc) 00 (nibble mode) 6 6 0 16 01, 10 (byte mode) 3 3 + 3 2 12 1 the first four udws are always the id.
adv7180 data sheet rev. g | page 60 of 120 i 2 c interface dedicated i 2 c readback registers are available for ccap, cgms, wss, gemstar, vps, pdc/utc, and vitc. because t eletext is a high data rate standard, data extraction is supported only through the ancillary data packet. user interface for i 2 c readback registers the vdp decodes all enabled vbi data standards in real time. because the i 2 c access speed is much lower th an the decoded rate, when the registers are accessed, they may be updated with data from the next line. to avoid this, vdp has a self -clearing clear bit and an available (avl) status bit accompanying all i 2 c readback registers. t he user must clear the i 2 c readback register by wr iting a high to the clear bit. t his resets the state of the available bit to low and indicates that the data in the associated readback registers is not valid. after the vdp decodes the next line of the corresponding vbi data, the d ecoded data is placed into the i 2 c readback register and the available bit is set to high to indicate that valid data is now available. though the vdp decodes this vbi data in subsequent lines if present, the decoded data is not updated to the readback reg isters until the clear bit is set high again. however, this data is available through the 656 ancillary data packets. the clear and available bits are in the vdp_status_clear (0x78, user sub map, write only) and vdp_status (0x78, user sub map, read only) r egisters, respectively. example i 2 c readback procedure the following tasks must be performed to read one packet (line) of pdc data from the decoder: 1. write 10 to i 2 c_gs_vps_pdc_utc[1:0] (0x9c, user sub map) to specify that pdc data must be updated to i 2 c registers. 2. write high to the gs_pdc_vps_utc_clear bit (0x78, user sub map) to enable i 2 c register updating. 3. poll the gs_pdc_vps_utc_avl bit (0x78, user sub map) going high to check the availability of the pdc packets. 4. read the data bytes from the pdc i 2 c re gisters. repeat step 1 to step 3 to read another line or packet of data. to read a packet of ccap, cgms, or wss data, step 1 to step 3 are required only because they have dedicated registers. vdp content- based data update for certain standards, such as w ss, cgms, gemstar, pdc, utc, and vps, the information content in the signal transmitted remains the same over numerous lines, and the user may want to be notified only when there is a change in the information content or loss of the information content. th e user must enable content - based updating for the required standard through the gs_vps_pdc_ utc_cb_change and wss_cgms_cb_change bits. therefore, the available bit shows the availability of that standard only when its content has changed. content - based up dating also applies to lines with lost data. therefore, for standards like vps, gemstar, cgms, and wss, if no data arrives in the next four lines programmed, the corresponding available bit in the vdp_status register is set high and the content in the i 2 c registers for that standard is set to 0. the user must write high to the corresponding clear bit so that when a valid line is decoded after some time, the decoded results are available in the i 2 c registers, with the available status bit set high. if conten t- based updating is enabled, the available bit is set high (assuming the clear bit was written) in the following cases: ? the data contents have changed. ? data was being decoded and four lines with no data have been detected. ? no data was being decoded and new data is now being decoded. gs_vps_pdc_utc_cb_change, enable content - based updating for gemstar/vps/pdc/utc, address 0x9c[5], user sub map setting gs_vps_pdc_utc_cb_change to 0 disables content - based updating. setting gs_vps_pdc_utc_cb_change to 1 (defau lt) enables content - based updating. wss_cgms_cb_change, enable content - based updating for wss/cgms, address 0x9c[4], user sub map setting wss_cgms_cb_change to 0 disables content - based updating. setting wss_cgms_cb_change to 1 (default) enables content - based updating. vdp interrupt- based reading of vdp i 2 c registers some vdp status bits are also linked to the interrupt request controller so that the user does not have to poll the available status bit. the user can configure the video decoder to trigger an interrupt request on the intrq pin in response to the valid data available in the i 2 c registers. this function is available for the following data types: ? cgms or wss . the user can select either triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. selection is made via the wss_cgms_cb_ change bit. ? gemstar, pdc, vps, or utc . the user can select to trigger an interrupt request each time sliced data is a vailable or to trigger an interrupt request only when the sliced data has changed. selection is made via the gs_vps_pdc_utc_ cb_change bit.
data sheet adv7180 rev. g | page 61 of 120 the sequence for the interrupt - based reading of the vdp i 2 c data registers is as follows for the ccap standard: 1. t he user unmasks the ccap interrupt mask bit ( register 0x50 , bit 0, user sub map = 1). ccap data occurs on the incoming video. vdp slices ccap data and places it into the vdp readback registers. 2. the vdp ccap available bit cc_cap goes high, and the vdp modul e signals to the interrupt controller to stimulate an interrupt request (for ccap in this case). 3. the user reads the interrupt status bits (user sub map) and sees that new ccap data is available ( register 0x4e , bit 0, user sub map = 1). 4. the user writes 1 to the ccap interrupt clear bit ( register 0x4f , bit 0, user sub map = 1) in the interrupt i 2 c space (this is a self- clearing bit). this clears the interrupt on the intrq pin but does not have an effect in the vdp i 2 c area. 5. the user reads th e ccap data from the vdp i 2 c area. 6. the user writes to bit cc_clear in the vdp_status_clear register, ( register 0x78 , bit 0, user sub map = 1) to signify the ccap data has been read (therefore the vdp ccap can be updated at the next occurrence of ccap). 7. th e user goes back to step 2. interrupt mask register details the following bits set the interrupt mask on the signal from the vdp vbi data slicer. vdp_ccapd_msk , address 0x50[0], user sub map setting vdp_ccapd_msk to 0 ( default) disables the interrupt on the vdp_ccapd_q signal. setting vdp_ccapd_msk to 1 enables the interrupt on the vdp_ccapd_q signal. vdp_cgms_wss_chngd_msk , address 0x50[2], user sub map setting vdp_cgm s_wss_chngd_msk to 0 (default) disables the interrupt on the vdp_cgms_wss_ chngd_q signal. setting vdp_cgms_wss_chngd_msk to 1 enables the interrupt on the vdp_cgms_wss_chngd_q signal. vdp_gs_vps_pdc_utc_chng_msk , add ress 0x50[4], user sub map setting vdp_gs_vps_pdc_utc_chng_msk to 0 (default) disables the interrupt on the vdp_gs_vps_pdc_utc_chng_q signal. setting vdp_gs_vps_pdc_utc_chng_msk to 1 enables the interrupt on the vdp_gs_ vps_pdc_utc_chng_q signal. vdp_vitc_msk , address 0x50[6], user sub map setting vdp_vitc_msk to 0 (default) disables the interrupt on the vdp_vitc_q signal. setting vdp_vitc_msk to 1 enables the interrup t on the vdp_vitc_q signal. interrupt status register details the following read - only bits contain data detection information from the vdp module since the status bit was last cleared or unmasked. vdp_ccapd_q, address 0x4e[0], user sub map when vdp_ccapd_ q is 0 (default), ccap data has not been detected. when vdp_ccapd_q is 1, ccap data has been detected. vdp_cgms_wss_chngd_q, address 0x4e[2], user sub map when vdp_cgms_wss_chngd_q is 0 (default), cgms or wss data has not been detected. when vdp_cgms_wss_chngd_q is 1, cgm or wss data has been detected. vdp_gs_vps_pdc_utc_chng_q, address 0x4e[4], user sub map when vdp_gs_vps_pdc_utc_chng_q is 0 (default), gemstar, pdc, utc, or vps data has not been detected. when vdp_gs_vps_pdc_utc_chng_q is 1, gemstar, p dc, utc, or vps data has been detected. vdp_vitc_q, address 0x4e[6], user sub map, read only when vdp_vitc_q is 0 (default), vitc data has not been detected. when vdp_vitc_q is 1, vitc data has been detected. interrupt status clear register details it is not nece ssary to write 0 to these write - only bits because they automatically reset after they have been set to 1 (self - clearing). vdp_ccapd_clr, address 0x4f[0], user sub map setting vdp_ccapd_clr to 1 clears the vdp_ccap_q bit. vdp_cgms_wss_chngd_clr, address 0x4f[2], user sub map setting vdp_cgms_wss_chngd_clr to 1 clears the vdp_cgms_wss_chngd_q bit. vdp_gs_vps_pdc_utc_chng_clr, address 0x4f[4], user sub map setting vdp_gs_vps_pdc_utc_chng_clr to 1 clears the vdp_gs_vps_pdc_utc_chng_q bit. vdp_vitc_clr, address 0x4f[6], user sub map setting vdp_vitc_clr to 1 clears the vdp_vitc_q bit.
adv7180 data sheet rev. g | page 62 of 120 i 2 c readback registers teletext because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. however, a ttxt_avl bit has been provided in i 2 c so that the user can check whether the vdp has detected teletext. note that the ttxt_avl bit is a plain status bit and does not use the protocol identified in the i 2 c interface section. ttxt_avl, teletext detected status, address 0x78[7], user sub map, read only when ttxt_avl is 0, teletext was not detected. when ttxt_avl is 1, teletext was detected. wst packet decoding for wst only, the vdp decodes the magazine and row address of teletext packets and further decodes the packets 8 4 hamming coded words. this feature can be disabled using the wst_pkt_decode_disable bit (bit 3, register 0x60, user sub map). this feature is valid for wst only. wst_pkt_decode_disable, disable hamming decoding of bytes in wst, address 0x60[3], user sub map setting wst_pkt_decode_disable to 0 enables hamming decoding of wst packets. setting wst_pkt_decode_disable to 1 (default) disables hamming decoding of wst packets. for hamming-coded bytes, the dehammed nibbles are output along with some error information from the hamming decoder as follows: ? input hamming coded byte: {d3, p3, d2, p2, d1, p1, d0, p0} (bits in decoded order) ? output dehammed byte: {e1, e0, 0, 0, d3', d2', d1', d0'} (di' C corrected bits, ei error information). table 79. error bits in the dehammed output byte e[1:0] error information output data bits in nibble 00 no errors detected okay 01 error in p4 okay 10 double error bad 11 single error found and corrected okay table 80 describes the wst packets that are decoded. table 80. wst packet description packet byte description header packet (x/00) 1 st magazine numberdehammed byte 4 2 nd row numberdehammed byte 5 3 rd page numberdehammed byte 6 4 th page numberdehammed byte 7 5 th to 10 th control bytesdehammed byte 8 to byte 13 11 th to 42 nd raw data bytes text packets (x/01 to x/25) 1 st magazine numberdehammed byte 4 2 nd row numberdehammed byte 5 3 rd to 42 nd raw data bytes 8/30 (format 1) packet 1 st magazine numberdehammed byte 4 design code = 0000 or 0001 2 nd row numberdehammed byte 5 utc 3 rd design codedehammed byte 6 4 th to 10 th dehammed initial teletext page, byte 7 to byte 12 11 th to 23 rd utc bytesdehammed byte 13 to byte 25 24 th to 42 nd raw status bytes 8/30 (format 2) packet 1 st magazine numberdehammed byte 4 design code = 0010 or 0011 2 nd row numberdehammed byte 5 pdc 3 rd design codedehammed byte 6 4 th to 10 th dehammed initial teletext page, byte 7 to byte 12 11 th to 23 rd pdc bytesdehammed byte 13 to byte 25 24 th to 42 nd raw status bytes x/26, x/27, x/28, x/29, x/30, x/31 1 1 st magazine numberdehammed byte 4 2 nd row numberdehammed byte 5 3 rd design codedehammed byte 6 4 th to 42 nd raw data bytes 1 for x/26, x/28, and x/29, further decoding needs 24 18 hamming decoding. not supported at present.
data sheet adv7180 rev. g | page 63 of 120 cgms and wss the cgms and wss data packets convey the same type of information for different video standards. wss is for pal and cgms is for ntsc; therefore, the cgms and wss readback registers are shared. wss is biphase coded; the vdp performs a biphase decoding to produce the 14 raw wss bits in the cgms/ wss readback i 2 c registers and to set the cgms_wss_avl bit. cgms_wss_clear, cgms/wss clear, address 0x78[2], user sub map, write only, self-clearing setting cgms_wss_clear to 1 reinitializes the cgms/wss readback registers. cgms_wss_avl, cgms/wss available, address 0x78[2], user sub map, read only when cgms_wss_avl is 0, cgms/wss was not detected. when cgms_wss_avl is 1, cgms/wss was detected. vdp_cgms_wss_data_0[3:0], address 0x7d[3:0]; vdp_cgms_wss_data_1[7:0], address 0x7e[7:0]; vdp_cgms_wss_data_2[7:0], address 0x7f[7:0]; user sub map, read only these bits hold the decoded cgms or wss data. refer to figure 46 and figure 47 for the i 2 c-to-wss and i 2 c-to- cgms bit mapping. 0 5700-039 active video v dp_cgms_wss_ data_1[5:0] vdp_cgms_wss_data_2 run-in sequence start code 0 1 2 3 4 5 6 7 0 1 2 3 4 5 11.0s 38.4s 42.5s figure 46. wss waveform 05700-040 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 vdp_cgms_wss_data_1 vdp_cgms_wss_ data_0[3:0] vdp_cgms_wss_data_2 ref +100 ire +70 ire 0 ire ?40 ire 11.2s 49.1s 0.5s crc sequence 2.235s 20ns figure 47. cgms waveform table 81. cgms readback registers 1 signal name register location address (user sub map) cgms_wss_data_0[3:0] vdp_cgms_wss_data_0[3:0] 125 0x7d cgms_wss_data_1[7:0] vdp_cgms_wss_data_1[7:0] 126 0x7e cgms_wss_data_2[7:0] vdp_cgms_wss_data_2[7:0] 127 0x7f 1 these registers are readback registers; default value does not apply.
adv7180 data sheet rev. g | page 64 of 120 ccap two bytes of decoded closed caption data are available in the i 2 c registers. the field information of the decoded ccap data can be obtained from the cc_even_field bit (register 0x78). cc_clear, closed caption clear, address 0x78[0], user su b map, write only, self - clearing setting cc_clear to 1 reinitializes the ccap readback registers. cc_avl, closed caption available, address 0x78[0], user sub map, read only when cc_avl is 0, closed captioning was not detected. when cc_avl is 1, closed capt ioning was detected. cc_even_field, address 0x78[1], user sub map, read only identifies the field from which the ccap data was decoded. when cc_even_field is 0, closed captioning was detected from an odd field. when cc_even_field is 1, closed captioning was detected from an even field. vdp_ccap_data_0, address 0x79[7:0], user sub map, read only decoded byte 1 of ccap data. vdp_ccap_data_1, address 0x7a[7:0], user sub map, read only decoded byte 2 of ccap data. 0 reference color burst (9 cycles) frequenc y = f sc = 3.579545mhz amplitude = 40 ire 1 7 cycles of 0.5035mhz (clock run-in) 2 3 4 5 6 7 0 1 2 3 4 5 6 7 p a r i t y s t a r t p a r i t y vdp_ccap_d at a_0 33.764s 10.003s 10.5 0.25s 12.91s 27.382s 50 ire 40 ire 05700-041 vdp_ccap_d at a_1 figure 48 . cca p waveform and decoded data correlation table 82 . ccap readback registers 1 signal name register location address (user sub map) ccap_byte_1[7:0] vdp_ccap_data_0[7:0] 121 0x79 ccap_byte_2[7:0] vdp_ccap_data_1[7:0] 122 0x7a 1 these registers are readback registers; default value does not apply.
data sheet adv7180 rev. g | page 65 of 120 v itc vit c has a sequence of 10 syncs between each data byte. the vdp strips these syncs from the data stream to output only the data bytes. the vitc results are available in register vdp_vitc_data_0 to register vdp_vitc_data_8 (r egister 0x92 to register 0x9 a, u ser s ub m ap). the vitc has a crc byte at the end; the syncs in between each data byte are also used in this crc calculation. because the syncs in between each data byte are not output, the crc is calculated internally. the calculated crc is available f or the user in the vdp_vitc_cal c_crc register (resister 0x9b, u ser s ub m ap). when the vdp completes decoding the vitc line, the vitc_data_x and vitc_crc registers are updated and the vitc_avl bit is set. vitc_clear, vitc clear, address 0x78[6], user sub map, write only, self - clearing setting vitc_clear to 1 reinitializes the vitc readback registers. vitc_avl, vitc available, address 0x78[6], user sub map, read only when vitc_avl is 0, vitc data was not detected. when vitc_avl is 1, vitc data was detected . vitc readback registers see figure 49 for the i 2 c- to - vitc bit mapping. bit 0, bit 1 bit 88, bit 89 to vitc waveform 05700-042 figure 49 . vitc waveform and decoded data correlation table 83 . vitc readback registe rs 1 signal name register location address (user sub map) vitc_data_0[7:0] vdp_vitc_data_0[7:0] (vitc bits[9:2]) 146 0x92 vitc_data_1[7:0] vdp_vitc_data_1[7:0] (vitc bits[19:12]) 147 0x93 vitc_data_2[7:0] vdp_vitc_data_2[7:0] (vitc bits[29:22]) 148 0x94 vitc_data_3[7:0] vdp_vitc_data_3[7:0] (vitc bits[39:32]) 149 0x95 vitc_data_4[7:0] vdp_vitc_data_4[7:0] (vitc bits[49:42]) 150 0x96 vitc_data_5[7:0] vdp_vitc_data_5[7:0] (vitc bits[59:52]) 151 0x97 vitc_data_6[7:0] vdp_vitc_data_6[7:0] (vitc bits[69:6 2]) 152 0x98 vitc_data_7[7:0] vdp_vitc_data_7[7:0] (vitc bits[79:72]) 153 0x99 vitc_data_8[7:0] vdp_vitc_data_8[7:0] (vitc bits[89:82]) 154 0x9a vitc_crc[7:0] vdp_vitc_calc_crc[7:0] 155 0x9b 1 the se registers are readback registers; default value does not apply.
adv7180 data sheet rev. g | page 66 of 120 vps/pdc/utc/gemstar the readback registers for vps, pdc, and utc are shared. gemstar is a high data rate standard and is available only through the ancillary stream. however, for evaluation purposes, any one line of gemstar is available through the i 2 c registers sharing the same register space as pdc, utc, and v ps. therefore, only vps, pdc, utc, or gemstar can be read through the i 2 c at one time. to identify the data that should be made available in the i 2 c registers, the user must program i 2 c_gs_vps_pdc_utc[1:0] (register address 0x9c, user sub map). i 2 c_gs_vps_ pdc_utc[1:0] (vdp), address 0x9c[7:6], user sub map specifies which standard result is available for i 2 c readback. gs_pdc_vps_utc_clear, gs/pdc/vps/utc clear, address 0x78[4], user sub map, write only, self - clearing setting gs_pdc_vps_utc_clear to 1 reinit ializes the gs/pdc/vps/utc data readback registers. gs_pdc_vps_utc_avl, gs/pdc/vps/utc available, address 0x78[4], user sub map, read only when gs_pdc_vps_utc_avl is 0, no gs, pdc, vps, or utc data was detected. when gs_pdc_vps_utc_avl is 1, one gs, pdc, vps, or utc data was detected. vdp_gs_vps_pdc_utc, readback registers, address 0x84 to address 0x90 see table 85 for information on the readback registers. vps the vps data bits are biphase decoded by the vdp. the decoded data is available in both the ancillary stream and in the i 2 c readback registers. vps decoded data is available in the vdp_gs_vps_pdc_utc_0 to vdp_vps_pdc_utc_12 registers (address 0x84 to address 0x90, user su b map). the gs_pdc_vps_utc_avl bit is set if the user programmed i 2 c_gs_vps_pdc_utc to 01, as explained in table 84 . gemstar the gemstar - decoded data is made available in the ancillary stream, and any one line of gemstar is also available in the i 2 c registers for evaluation purposes. to read gemstar results through the i 2 c registers, the user must program i 2 c_gs_vps_pdc_utc to 00, as explained in table 84. table 84. i 2 c_gs_vps_pdc_ utc[1:0] function i 2 c_gs_vps_pdc_utc[1:0] description 00 (default) gemstar 1/2 01 vps 10 pdc 11 utc vdp supports autodetection of the gemstar standard, either gemstar 1 or gemstar 2, and decodes accordingly. for the autodetection mode to work, t he user must set the auto_detect_gs_type bit (register 0x61, user sub map) and program the decoder to decode gemstar 2 on the required lines through line programming. the type of gemstar decoded can be determined by observing the gs_data _type bit (registe r 0x78, u ser s ub m ap). auto_detect_gs_type, address 0x61[4], user sub map setting auto_detect_gs_type to 0 (default) disables the autodetection of the gemstar type. setting auto_detect_gs_type to 1 enables the autodetection of the gemstar type. gs_data_t yp e, address 0x78[5], user sub map, read only identifies the decoded gemstar data type. when gs_data_type is 0, gemstar 1 mode is detected. read two data bytes from 0x84. when gs_data_type is 1, gemstar 2 mode is detected. read four data bytes from 0x84. t he gemstar data that is available in the i 2 c register can be from any line of the input video on which gemstar was decoded. to read the gemstar data on a particular video line, the user should use the manual configuration described in table 70 and table 71 and enable gemstar decoding only on the required line. pdc/utc pdc and utc are data transmitted through teletext packet 8/30 format 2 (magazine 8, row 30, design c ode 2 or design code 3) and packet 8/30 format 1 (magazine 8, row 30, design code 0 or design code 1). therefore, if pdc or utc data is to be read through i 2 c, the corresponding teletext standard (wst or pal system b) should be decoded by vdp. the whole te letext decoded packet is output on the ancillary data stream. the user can look for the magazine number, row number, and design code and qualify the data as pdc, utc, or neither of these. if pdc/utc packets are identified, byte 0 to byte 12 are updated to the vdp_gs_vps_pdc_utc_0 to vdp_vps_pdc_utc_12 registers , and the gs_pdc_vps_utc_avl bit is set. the full packet data is also available in the ancillary data format. note that the data available in the i 2 c register depends on the status of the wst_pkt_deco de_disable bit (bit 3, subaddress 0x60, user sub map).
data sheet adv7180 rev. g | page 67 of 120 table 85 . gs/vps/pdc/utc readback registers 1 signal name register location dec address (user sub map) hex address (user sub map) gs_vps_pdc_utc_byte_0[7:0] vdp_gs_vps_p dc_utc_0[7:0] 132 0x84 gs_vps_pdc_utc_byte_1[7:0] vdp_gs_vps_pdc_utc_1[7:0] 133 0x85 gs_vps_pdc_utc_byte_2[7:0] vdp_gs_vps_pdc_utc_2[7:0] 134 0x86 gs_vps_pdc_utc_byte_3[7:0] vdp_gs_vps_pdc_utc_3[7:0] 135 0x87 vps_pdc_utc_byte_4[7:0] vdp_vps_pdc_utc_4[7 :0] 136 0x88 vps_pdc_utc_byte_5[7:0] vdp_vps_pdc_utc_5[7:0] 137 0x89 vps_pdc_utc_byte_6[7:0] vdp_vps_pdc_utc_6[7:0] 138 0x8a vps_pdc_utc_byte_7[7:0] vdp_vps_pdc_utc_7[7:0] 139 0x8b vps_pdc_utc_byte_8[7:0] vdp_vps_pdc_utc_8[7:0] 140 0x8c vps_pdc_utc_by te_9[7:0] vdp_vps_pdc_utc_9[7:0] 141 0x8d vps_pdc_utc_byte_10[7:0] vdp_vps_pdc_utc_10[7:0] 142 0x8e vps_pdc_utc_byte_11[7:0] vdp_vps_pdc_utc_11[7:0] 143 0x8f vps_pdc_utc_byte_12[7:0] vdp_vps_pdc_utc_12[7:0] 144 0x90 1 the default value does not apply to readback registers. vbi system 2 the user has an opti on of using a different vbi data slicer called vbi system 2. this data slicer is used to decode gemstar and closed caption vbi signals only. using this system, the gemstar data is available only in the ancillary data stream. a special mode enables one line of data to be read back through i 2 c. gemstar data recovery the gemstar - compatible data recovery block (gscd) supports 1 and 2 data transmissions. in addition, it can serve as a closed caption decoder. gemstar - compatible data transmissions can occur onl y in ntsc. closed caption data can be decoded in both pal and ntsc. the block can be configured via i 2 c as follows: ? gdecel[15:0] allows data recovery on selected video lines on even fields to be enabled or disabled. ? gdecol[15:0] enables the data recovery on selected lines for odd fields. ? gdecad[0] configures the way in which data is embedded in the video data stream. the recovered data is not available through i 2 c but is inserted into the horizontal blanking period of an itu - r bt.656 - compatible data stream. the data format is intended to comply with the recommendation by the international telecommunications union, itu - r bt.1364. for more information, visit the international telecommunication union website. see fig ure 50. gde_sel_old_adf, address 0x4c[3], user sub map the adv7180 has a new ancillary data output block that can be used by the vdp data slicer and the vbi system 2 data slicer. the new ancillary data formatter is used by setting gde_sel_old_adf to 0 (default). see table 74 and table 75 for information about how the data is packaged in the ancillary data stream when this bit is set low . to use the old ancillary data formatter (to be backward compatible with the adv7183b ), set gde_sel_old_adf to 1. the ancillary data format in this section refers to the adv7183b - compatible ancillary data formatter. setting gde_sel_old_adf to 0 (default) enables a new ancillary data system for use with the vdp and vbi system 2. setting gde_sel_old_adf to 1 enables the old ancillary data system for use with the vbi system 2 only (adv7183b com patible). the format of the data packet depends on the following criteria: ? transmission is 1 or 2. ? data is output in 8 - bit or 4 - bit format (see the description of the bit). ? data is closed caption (ccap) or gemstar compatible. data packets are output if t he corresponding enable bit is set (see the gdecel[15:0], gemstar decoding even lines, address 0x48[7:0], address 0x49[7:0] and the gdecol[15:0], gemstar decoding odd line s, address 0x4a[7:0], address 0x4b[7:0] section s) , and the decoder detects the presence of data. for video lines where no data is decoded, no data packet is output, even if the corresponding line enable bit is set.
adv7180 data sheet rev. g | page 68 of 120 each data packet starts immediately after the eav code of the preceding line. figure 50 and table 86 show the overall structure of the data packet. entries within the packet are as follows: ? fixed preamble sequence of 0x00, 0xff, and 0xff. ? did. the value for the did marking a gemstar or ccap data packet is 0x140 (10 - bit value). ? sdid, which contains information about the video line from which data was retrieved, whether the gemstar transmission was in 1 or 2 format, and whether it was retrieved from an even or odd field. ? data count byte, giving the number of user data - words that follow. ? user data section. ? optional padding to ensure that the length of the user data - word section of a packet is a multiple of f our bytes (requirement as set in itu - r bt.1364). ? checksum byte. table 86 lists the values within a generic data packet that is output by the adv7180 in 8 - bit format. 05700-043 00 ff ff did sdid data co un t user data opt io nal p add ing byt es ch eck sum seco nd ary data i dentificat io n preamble for anc i ll ary data d a ta i dentificat io n user data (4 o r 8 wo rd s) figure 50 . gemst ar- and ccap - embedded data packet (generic) table 86 . generic data output packet byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 2x line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 dc[1] dc[0] 0 0 data count (dc) 6 ep ep 0 0 word1[7:4] 0 0 user data - words 7 ep ep 0 0 word1[3:0] 0 0 user data - words 8 ep ep 0 0 word2[7:4] 0 0 user data - words 9 ep ep 0 0 word2[3:0] 0 0 user data - words 10 ep ep 0 0 word3[7:4] 0 0 user data - words 11 ep ep 0 0 word3[3:0] 0 0 user data - words 12 ep ep 0 0 word4[7:4] 0 0 user data - words 13 ep ep 0 0 word4[3:0] 0 0 user data - words 14 cs[8] cs[8] cs [7] cs[6] cs[5] cs[4] cs[3] cs[2] 0 0 checksum table 87 . data byte allocation 2 raw information bytes retrieved from the video line gdecad user data - words (including padding) padding bytes dc[1:0] 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01
data sheet adv7180 rev. g | page 69 of 120 gemstar bit names the following are the gemstar bit names: ? did the data identification value is 0x140 (10 - bit value). care has been taken so that in 8 - bit systems, the two lsbs do not carry vital information. ? ep and ep the ep bit is set to ensure even parity on the d[8:0] data - word . even parity means there is always an even number of 1s within the d[8:0] bit arrangement. this includes the ep bit. ep describes the logic inverse of ep and is output on d[9]. the ep is output to ensure that the reserved codes of 00 and ff do not occur. ? ef even field identifier. ef = 1 indicates that the data was recovered from a video line on an even field. ? 2 this bit indicates whether the data sliced was in gemstar 1 or 2 format. a high indicates 2 format. the 2 bit determines whether the raw information retrieved from the video line was two bytes or four bytes. the state of the gdecad bit affects whether the bytes are transmi tted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). padding bytes are then added where necessary. ? line[3:0] this entry provides a code that is unique for ea ch of the possible 16 source lines of video from which gemstar data may have been retrieved. refer to table 96 and table 97. ? dc[1:0] data count value. the number of udw s in the packet divided by 4. the number of udws in any packet must be an integral number of 4. padding may be required at the end, as set in itu -r bt.1364. see table 87 . ? cs[8:2] the checksum is provided to dete rmine the integrity of the ancillary data packet. it is calculated by summing up d[8:2] of did, sdid, the data count byte, and all udws and ignoring any overflow during the summation. because all data bytes that are used to calculate the checksum have thei r two lsbs set to 0, the cs[1:0] bits are also always 0. cs [8] describes the logic inversion of cs[8]. the value cs [8] is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and 0xff do not occur. table 88 to table 91 outline the possible data packages. gemstar_2 format, half - byte output mode half - byte output mode is selected by setting gdecad to 0; full- byte output mode is selected by setting gdecad to 1. see the gdecad, gemstar decode ancillary data format, address 0x4c[0] section. gemstar_1 format half - byte output mode is selected by setting cdecad to 0, full - byte output mode is selected by setting cdecad to 1. see the gdecad, gemstar decode ancillary data format, address 0x4c[0] section. table 88 . gemstar_2 data, half - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 1 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 1 0 0 0 data count 6 ep ep 0 0 gemstar word1[7:4] 0 0 user data - words 7 ep ep 0 0 gemstar word1[3:0] 0 0 user data - words 8 ep ep 0 0 gemstar word2[7:4] 0 0 user data - words 9 ep ep 0 0 gemstar word2[3:0] 0 0 user data - words 10 ep ep 0 0 gemstar word3[7:4] 0 0 user data - words 11 ep ep 0 0 gemstar word3[3:0] 0 0 user data - wor ds 12 ep ep 0 0 gemstar word4[7:4] 0 0 user data - words 13 ep ep 0 0 gemstar word4[3:0] 0 0 user data - words 14 cs [8] cs[8] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum
adv7180 data sheet rev. g | page 70 of 120 ta ble 89 . gemstar_2 data, full - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 1 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 gemstar word1[7:0] 0 0 user data - words 7 gemstar word2[7:0] 0 0 user data - words 8 gemstar word3[7:0] 0 0 user data - words 9 gemstar word4[7:0] 0 0 user data - words 10 cs [8] cs[8] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum table 90 . gemstar_1 data, half - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ep ep 0 0 gemstar word1[7:4] 0 0 user data - words 7 ep ep 0 0 gemstar word1[3:0] 0 0 user data - words 8 ep ep 0 0 gemstar word2[7:4] 0 0 user data - words 9 ep ep 0 0 gemstar word2[3:0] 0 0 user data - words 10 cs [8] cs[8] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum table 91 . gemstar_1 data, full - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 line[3:0] 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 gemstar word1[7:0] 0 0 user data - words 7 gemstar word2[7:0] 0 0 user data - words 8 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 9 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 10 cs [8] cs[8] cs[7] cs[6] c s[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum
data sheet adv7180 rev. g | page 71 of 120 table 92 . ntsc ccap data, half - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 1 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ep ep 0 0 ccap word1[7:4] 0 0 user data - words 7 ep ep 0 0 ccap word1[3:0] 0 0 user data - words 8 ep ep 0 0 ccap word2[7:4] 0 0 user data - words 9 ep ep 0 0 ccap word2[3:0] 0 0 user data - words 10 cs [8] cs[8] cs[7] cs [6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum table 93 . ntsc ccap data, full - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamb le 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 1 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ccap word1[7:0] 0 0 user data - words 7 ccap word2[7:0] 0 0 user data - wor ds 8 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 9 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 10 cs [8] cs[8] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum
adv7180 data sheet rev. g | page 72 of 120 table 94 . pal ccap data, half - byte mode byte d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 0 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ep ep 0 0 ccap word1[7:4] 0 0 user data - words 7 ep ep 0 0 ccap word1[3:0] 0 0 user data - words 8 ep ep 0 0 ccap word2[7:4] 0 0 user data - words 9 ep ep 0 0 ccap word2[3:0] 0 0 user data - words 10 cs [8] cs[8] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum table 95 . pal ccap data, full - byte mode byte d [9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] description 0 0 0 0 0 0 0 0 0 0 0 fixed preamble 1 1 1 1 1 1 1 1 1 1 1 fixed preamble 2 1 1 1 1 1 1 1 1 1 1 fixed preamble 3 0 1 0 1 0 0 0 0 0 0 did 4 ep ep ef 0 1 0 1 0 0 0 sdid 5 ep ep 0 0 0 0 0 1 0 0 data count 6 ccap word1[7:0] 0 0 user data - words 7 ccap word2[7:0] 0 0 user data - words 8 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 9 1 0 0 0 0 0 0 0 0 0 udw padding 0x200 10 cs [8] cs[8 ] cs[7] cs[6] cs[5] cs[4] cs[3] cs[2] cs[1] cs[0] checksum ntsc ccap data half - byte output mode is selected by setting gdecad to 0, and the full - byte mode is enabled by setting gdecad to 1. see the gdecad, gems tar decode ancillary data format, address 0x4c[0] section. the data packet formats are shown in table 92 and table 93 . only closed caption data can be embedded in the ou tput data stream. ntsc closed caption data is sliced on line 21 of even and odd fields. the corresponding enable bit must be set high. see the gdecad, gemstar decode ancillary data format, address 0x4c[0] section and the gdecol[15:0], gemstar decoding odd lines, address 0x4a[7:0], address 0x4b[7:0] section. pal ccap data half - byte output mode is selected by setting gdecad to 0, and full - byte output mode is selected by se tting gdecad to 1. see the gdecad, gemstar decode ancillary data format, address 0x4c[0] section . table 94 and table 95 list t he bytes of the data packet. only closed caption data can be embedded in the output data stream. pal closed caption data is sliced from line 22 and line 335. the corresponding enable bits must be set. see the gdece l[15:0], gemstar decoding even lines, address 0x48[7:0], address 0x49[7:0] section and the gdecol[15:0], gemstar decoding odd lines, address 0x4a[7:0], address 0x4b[7:0] section. gdecel[15:0], gemstar decoding e ven lines, address 0x48[7:0], address 0x49[7:0] the 16 bits of gdecel[15:0] are interpreted as a collection of 16 individual line decode enable signals. each bit refers to a line of video in an even field. setting the bit enables the decoder block trying t o find gemstar or closed caption - compatible data on that particular line. setting the bit to 0 prevents the decoder from trying to retrieve data. see table 96 and table 97 . to retrieve closed caption data services on ntsc (line 284), gdecel[11] must be set. to retrieve closed caption data services on pal (line 335), gdecel[14] must be set. the default value of gdecel[15:0] is 0x0000. this setting instructs the decoder not to attempt to decode gemstar or ccap data from any line in the even field. the user should only enable gemstar slicing on lines where vbi data is expected.
data sheet adv7180 rev. g | page 73 of 120 table 96 . ntsc line enable bits and corresponding line numbering line[3:0 ] line number (itu -r bt.470) enable bit comment 0 10 gdecol[0] gemstar 1 11 gdecol[1] gemstar 2 12 gdecol[2] gemstar 3 13 gdecol[3] gemstar 4 14 gdecol[4] gemstar 5 15 gdecol[5] gemstar 6 16 gdecol[6] gemstar 7 17 gdecol[7] gemstar 8 18 gdecol[8] gemstar 9 19 gdecol[9] gemstar 10 20 gdecol[10] gemstar 11 21 gdecol[11] gemstar or closed caption 12 22 gdecol[12] gemstar 13 23 gdecol[13] gemstar 14 24 gdecol[14] gemstar 15 25 gdecol[15] gemstar 0 273 (10) gdecel[0] gemstar 1 274 (11) gdecel[1 ] gemstar 2 275 (12) gdecel[2] gemstar 3 276 (13) gdecel[3] gemstar 4 277 (14) gdecel[4] gemstar 5 278 (15) gdecel[5] gemstar 6 279 (16) gdecel[6] gemstar 7 280 (17) gdecel[7] gemstar 8 281 (18) gdecel[8] gemstar 9 282 (19) gdecel[9] gemstar 10 28 3 (20) gdecel[10] gemstar 11 284 (21) gdecel[11] gemstar or closed caption 12 285 (22) gdecel[12] gemstar 13 286 (23) gdecel[13] gemstar 14 287 (24) gdecel[14] gemstar 15 288 (25) gdecel[15] gemstar gdecol[15:0], gemstar decoding odd lines, address 0 x4a[7:0], address 0x4b[7:0] the 16 bits of gdecol[15:0] form a collection of 16 individual line decode enable signals. see table 96 and table 97. to retrieve closed capt ion data services on ntsc (line 21), gdecol[11] must be set. to retrieve closed caption data services on pal (line 22), gdecol[14] must be set. the default value of gdecol[15:0] is 0x0000. this setting instructs the decoder not to attempt to decode gemstar or ccap data from any line in the odd field. the user should only enable gemstar slicing on lines where vbi data is expected. gdecad, gemstar decode ancillary data format, address 0x4c[0] the decoded data from gemstar - compatible transmissions or closed c aption - compatible transmissions is inserted into the horizontal blanking period of the respective line of video. a potential problem can arise if the retrieved data bytes have a value of 0x00 or 0xff. in an itu - r bt.656 - compatible data stream, these values are reserved and used only to form a fixed preamble. the gdecad bit allows the data to be inserted into the horizontal blanking period in two ways: ? insert all data straight into the data stream, even the reserved values of 0x00 and 0xff, if they occur. th is may violate output data format specification itu - r bt.1364. ? split all data into nibbles and insert the half - bytes over double the number of cycles in a 4 - bit format. when gdecad is 0 (default), the data is split into half - bytes and inserted. when gdecad is 1, t he data is output straight into the data stream in 8 - bit format . table 97 . pal line enable bits and line numbering line[3:0] line number (itu - r bt.470) enable bit comment 12 8 gdecol[0] not valid 13 9 gdecol[1] not valid 14 10 gdecol[2] not valid 15 11 gdecol[3] not valid 0 12 gdecol[4] not valid 1 13 gdecol[5] not valid 2 14 gdecol[6] not valid 3 15 gdecol[7] not valid 4 16 gdecol[8] not valid 5 17 gdecol[9] not valid 6 18 gdecol[10] not valid 7 19 gdecol[11] not valid 8 20 gdecol[12] not valid 9 21 gdecol[13] not valid 10 22 gdecol[14] closed caption 11 23 gdecol[15] not valid 12 321 (8) gdecel[0] not valid 13 322 (9) gdecel[1] not valid 14 323 (10) gdecel[2] not valid 15 324 (11) gdecel[3] not valid 0 3 25 (12) gdecel[4] not valid 1 326 (13) gdecel[5] not valid 2 327 (14) gdecel[6] not valid 3 328 (15) gdecel[7] not valid 4 329 (16) gdecel[8] not valid 5 330 (17) gdecel[9] not valid 6 331 (18) gdecel[10] not valid 7 332 (19) gdecel[11] not valid 8 333 (20) gdecel[12] not valid 9 334 (21) gdecel[13] not valid 10 335 (22) gdecel[14] closed caption 11 336 (23) gdecel[15] not valid
adv7180 data sheet rev. g | page 74 of 120 letterbox detection incoming video signals may conform to different aspect ratios (16:9 wide screen or 4:3 standard). for certain transmissions in the wide - screen format, a digital sequence (wss) is transmitted with the video signal. if a wss sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits that wss contains. in the absenc e of a wss sequence, letterbox detection can be used to find wide - screen signals. the detection algorithm examines the active video content of lines at the start and end of a field. if black lines are detected, this may indicate that the currently shown pi cture is in wide - screen format. the active video content (luminance magnitude) over a line of video is summed together. at the end of a line, this accumulated value is compared with a threshold, and a decision is made as to whether or not a particular line is black. the threshold value needed may depend on the type of input signal; some control is provided via lb_th[4:0]. detection at the start of a field the adv7180 expects a section of at least six consecutive black lines of video at the top of a field. a fter those lines are detected, lb_lct[7:0] reports the number of black lines that were actually found. by default, the adv7180 starts looking for those black lines in sync with the beginning of active video, for example, immediately after the last vbi vide o line. lb_sl[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line - by - line basis. the detection window closes in the middle of the field. detection at the end of a field the adv7180 expects at least six conti nuous lines of black video at the bottom of a field before reporting the number of lines actually found via the lb_lcb[7:0] value. the activity window for letterbox detection (end of field) starts in the middle of an active field. its end is programmable v ia lb_el[3:0]. detection at the midrange some transmissions of wide - screen video include subtitles within the lower black box. if the adv7180 finds at least two black lines followed by some more nonblack video, for example, the subtitle followed by the rem ainder of the bottom black block, it reports a midcount via lb_lcm[7:0]. if no subtitles are found, lb_lcm[7:0] reports the same number as lb_lcb[7:0]. there is a two - field delay in reporting any line count parameter. there is no letterbox detected bit. read the lb_lct[7:0] and lb_lcb[7:0] register values to determine whether the letterbox - type video is present in the software. lb_lct[7:0], letterbox line count top, address 0x9b[7:0]; lb_lcm[7:0], letterbox line count mid, address 0x9c[7:0]; lb_lcb[7:0], letterbox line count bottom, address 0x9d[7:0] table 98 . lb_lcx access information signal name address lb_lct[7:0] 0x9b lb_lcm[7:0] 0x9c lb_lcb[7:0] 0x9d lb_th[4:0], letterbox threshold control, address 0xdc[4:0] table 99 . lb_th function lb_th[4:0] description 01100 (default) default thresho ld for detection of black lines 01101 to 10000 increase threshold (need larger active video content bef ore identifying nonblack lines) 00000 to 01011 decrease thr eshold (even small noise levels can cause t he detection of nonblack lines) lb_sl[3:0], letterbox start line, address 0xdd[7:4] the lb_sl[3:0] bits are set at 0100 by default. for an ntsc signal, this window is from line 23 to line 286. by changing the bi ts to 0101, the detection window starts on line 24 and ends on line 287. lb_el[3:0], letterbox end line, address 0xdd[3:0] the lb_el[3:0] bits are set at 1101 by default. this means that the letterbox detection window ends with the last active video line. for an ntsc signal, this window is from line 262 to line 525. by changing the bits to 1100, the detection window starts on line 261 and ends on line 254.
data sheet adv7180 rev. g | page 75 of 120 pixel port configura tion the adv7180 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ics. table 100 , table 101 , and table 102 summarize the various functions that t he adv7180 pins can have in different modes of operation. the ordering of components, for example, cr vs. cb for channel a, channel b, and channel c can be changed. see the swpc, swap pixel cr/cb, address 0x27[7] section. table 100 indicates the default positions for the cr/cb components. of_sel[3:0], output format sel ection, address 0x03[5:2] the modes in which the adv7180 pixel port can be configured are under the cont rol of of_sel[3:0]. see table 102 for details. the default llc frequency output on the llc pin is approximately 27 mhz. for modes that operate with a nominal data rate of 13.5 mhz (0001, 0010), the clock frequen cy on the llc pin stays at the higher rate of 27 mhz. for information on outputting the nominal 13.5 mhz clock on the llc pin, see the llc_pad_sel[2:0] llc output selection, address 0x8f[6:4] s ection . swp c, swap pixel cr/cb, address 0x27[7] this bit allows cr and cb samples to be swapped. when swpc is 0 (default), no swapping is allowed. when swpc is 1, the cr and cb values can be swapped. llc_pad_sel[2:0] llc output selection, address 0x8f[6:4] the foll owing i 2 c write allows the user to select between llc (nominally at 27 mhz) and llc (nominally at 13.5 mhz). the llc signal is useful for llc - compatible wide bus (16 - bit) output modes. see the of_sel[3:0], output format sel ection , address 0x03[5:2] section for additional information. the llc signal and data on the data bus are synchronized. by default, the rising edge of llc/llc is aligned with the y data; the falling edge occurs when the data bus holds c data. t he polarity of the clock, and therefore the y/c assignments to the clock edges, can be altered by using the polarity llc pin. when llc_pad_sel is 000, the output is nominally 27 mhz llc on the llc pin (default). when llc_pad_sel is 101, the output is nomin ally 13.5 mhz llc on the llc pin. table 100 . 64 - lead lqfp p15 to p0 output/input pin mapping data port pins p[15:0] format and mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 video out, 8 - bit, 4:2:2 ycrcb[7:0]out video out, 16 -bi t, 4:2:2 y[7:0]out crcb[7:0]out table 101 . 48 - lead, 40 - lead , and 32 - lead d evices p7 to p0 output/input pin mapping data port pins p[7:0] format and mode 7 6 5 4 3 2 1 0 video out, 8 - bit, 4:2:2 ycrcb[7:0]out table 102 . adv7180 standard definition pixel port modes 64- lead lqfp p[15:0] 48- lead lqfp , 40- lead lfcsp , or 32- lead lfcsp of_sel[3:0] format p[15:8] p[7:0] p[7:0] 0000 to 0001 reserved reserved, do not use 0010 16- bit at llc 4:2:2 y[7:0] crcb[7 :0] not valid 0011 (default) 8- bit at llc 4:2:2 (default) ycrcb[7:0] three - state ycrcb[7:0] 0100 to 1111 reserved reserved, do not use
adv7180 data sheet rev. g | page 76 of 120 gpo control the 64 - lead and 48 - lead lqfp has four general - purpose outputs (gpo). these outputs allow the user to co ntrol other devices in a system via the i 2 c port of the device. the 40 - lead and 32 - lead lfcsp do not have gpo pins. gpo_e nable , general - purpose output enable, address 0x59[4] when gpo_e nable is set to 0, all gpo pins are three - stated. when gpo_e nable is s et to 1, all gpo pins are in a driven state. the polarity output from each gpo is controlled by gpo[3:0] for the 64 -l ead and 48 - lead lqfp . gpo[3:0], general - purpose outputs, address 0x59[3:0] individual control of the four gpo ports is achieved using gpo[ 3:0]. gpo_ enable must be set to 1 for the gpo pins to become active. gpo[0] when gpo[0] is set to 0, logic 0 is output from the gpo0 pin. when gpo[0] is set to 1, logic 1 is output from the gpo0 pin. gpo[1] when gpo[1] is set to 0, logic 0 is output from t he gpo1 pin. when gpo[1] is set to 1, logic 1 is output from the gpo1 pin. gpo[2] when gpo[2] is set to 0, logic is output from the gpo2 pin. when gpo[2] is set to 1, logic 1 is output from the gpo2 pin. gpo[3] when gpo[3] is set to 0, logic 0 is output fr om the gpo3 pin. when gpo[3] is set to 1, logic 1 is output from the gpo3 pin. table 103 . general - purpose output truth table gpo_enable gpo[3:0] gpo3 gpo2 gpo1 gpo0 0 xxxx 1 z z z z 1 0000 0 0 0 0 1 0001 0 0 0 1 1 0010 0 0 1 0 1 0011 0 0 1 1 1 0100 0 1 0 0 1 0101 0 1 0 1 1 0110 0 1 1 0 1 0111 0 1 1 1 1 1000 1 0 0 0 1 1001 1 0 0 1 1 1010 1 0 1 0 1 1011 1 0 1 1 1 1100 1 1 0 0 1 1101 1 1 0 1 1 1110 1 1 1 0 1 1111 1 1 1 1 1 x indicates any value.
data sheet adv7180 rev. g | page 77 of 120 mpu port description the adv7180 supports a 2-wire (i 2 c-compatible) serial interface. two inputs, serial data (sdata) and serial clock (sclk), carry information between the adv7180 and the system i 2 c master controller. each slave device is recognized by a unique address. the adv7180 i 2 c port allows the user to set up and configure the decoder and to read back the captured vbi data. the adv7180 has four possible slave addresses for both read and write operations, depending on the logic level of the alsb pin. the four unique addresses are shown in table 104. the adv7180 alsb pin controls bit 1 of the slave address. by altering the alsb, it is possible to control two adv7180s in an application without the conflict of using the same slave address. the lsb (bit 0) sets either a read or write operation. logic 1 corresponds to a read operation, and logic 0 corresponds to a write operation. table 104. i 2 c address for adv7180 alsb r/ w slave address 0 0 0x40 0 1 0x41 1 0 0x42 1 1 0x43 to control the device on the bus, a specific protocol must be followed. first, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition on sdata while sclk remains high. this indicates that an address/ data stream follows. all peripherals respond to the start condition and shift the next eight bits (the 7-bit address plus the r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sdata and sclk lines for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads information from the peripheral. the adv7180 acts as a standard slave device on the bus. the data on the sdata pin is eight bits long, supporting the 7-bit address plus the r/ w bit. the device has 249 subaddresses to enable access to the internal registers. it, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without updating all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclk high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7180 does not issue an acknowledge and returns to the idle condition. in auto-increment mode, if the user exceeds the highest subaddress, the following action is taken: ? in read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. this indicates the end of a read. a no acknowledge condition occurs when the sdata line is not pulled low on the ninth pulse. ? in write mode, the data for the invalid byte is not loaded into any subaddress register. a no acknowledge is issued by the adv7180, and the part returns to the idle condition. sdat a sclk start addr ack ack data ack stop subaddress 1?7 1?7 8 9 8 9 1?7 8 9 s p r/w 05700-044 figure 51. bus data transfer s write sequence slave addr a(s) sub addr a(s) data a(s) data a(s) p s read sequence slave addr slave addr a(s) sub addr a(s) s a(s) data a(m) data a(m) p s = start bit p=stopbit a(s) = acknowledge by slave a(m) = acknowledge by master a(s) = no acknowledge by slave a(m) = no acknowledge by master lsb = 1 lsb = 0 05700-045 figure 52. read and write sequence
adv7180 data sheet rev. e | page 78 of 120 register access the mpu can write to or read from all of the adv7180 registers except the subaddress r egister, which is write only. the subaddress register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the subaddress register. a read/write operation is then perf ormed from or to the target address, which increments to the next address until a stop command on the bus is performed. register programming the following sections describe the configuration for each register. the communication register is an 8 - bit, write - only register. after the part is accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to or from which register the operation takes place. ta ble 105 lists the various operations under the control of the subaddress register for the control port. sub_usr_en, address 0x0e[5] this bit splits the register map at register 0x40. common i 2 c sp ac e addr ess 0x00 0x3f addr ess 0x0 e bit 5 = 0b addr ess 0x0 e bit 5 = 1b i 2 c sp ac e addr ess 0x40 0x ff i 2 c sp ac e addr ess 0x40 0x9c user map user s ub map normal re gi ster sp ac e inte rru pt and vdp re gi ster sp ac e 05700-050 figure 53 . register access user map and user sub map register select (sr7 to sr0) these bits are set up to point to the required starting address. i 2 c sequencer an i 2 c sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more i 2 c registers, for example, hsb[ 10:0]. when such a parameter is changed using two or more i 2 c write operations, the parameter may hold an invalid value for the time between the first i 2 c being completed and the last i 2 c being completed. in other words, the top bits of the parameter may h old the new value while the remaining bits of the parameter still hold the previous value. to avoid this problem, the i 2 c sequencer holds the updated bits of the parameter in local memory, and all bits of the parameter are updated together once the last re gister write operation has completed. the correct operation of the i 2 c sequencer relies on the following: x all i 2 c registers for the parameter in question must be written to in order of ascending addresses. for example, for hsb[10:0], write to address 0x34 first, followed by 0x35, and so on. x no other i 2 c can take place between the two (or more) i 2 c writes for the sequence. for example, for hsb[10:0], write to address 0x34 first, immediately followed by 0x35, and so on.
data sheet adv7180 rev. e | page 79 of 120 i 2 c register maps table 105 . main register map details address reset dec hex register name rw 7 6 5 4 3 2 1 0 value (hex) 0 00 input c ontrol rw vid_sel[3] vid_sel[2] vid_sel[1] vid_sel[0] insel[3] insel[2] insel[1] insel[0] 00000000 00 1 01 video s elec tion rw enhspll betacam envsproc sqpe 11001000 c8 3 03 output c ontrol rw vbi_en tod of_sel[3] of_sel[2] of_sel[1] of_sel[0] sd_dup_av 00001100 0c 4 04 extended o utput c ontrol rw bt.656 -4 tim_oe bl_c_vbi en_sfl_pin range 01xx0101 45 5 05 reserved 6 06 reserved 7 07 autodetect e nable rw ad_sec525_en ad_secam_en ad_n443_en ad_p60_en ad_paln_en ad_palm_en ad_ntsc_en ad_pal_en 01111111 7f 8 08 contrast rw con[7] con[6] con[5] con[4] con[3] con[2] con[1] con[0] 10000000 80 9 09 reserved 10 0a brightness rw bri[7] bri[6] bri[5] bri[4] bri[3] bri[2] bri[1] bri[0] 00000000 00 11 0b hue rw hue[7] hue[6] hue[5] hue[4] hue[3] hue[2] hue[1] hue[0] 00000000 00 12 0c default value y rw def_y[5] def_y[4] def_y[3] def_y[2] def_y[1] def_y[0] def_val_ auto_en def_val_en 00110110 36 13 0d default value c rw def_c[7] def_c[6] def_c[5] def_c[4] def_c[3] def_c[2] def_c[1] def_c[0] 01111100 7c 14 0e adi control 1 rw sub_usr_en 00000000 00 15 0f power m anagement rw r eset pwrdwn pdbp 00000000 00 16 10 status 1 r col_kill ad_result[2] ad_result[1] ad_result[0] follow_pw fsc_lock lost_lock in_lock 17 11 ident r ident[7] ident[6] ident[5] ident[4] ident[3] ident[2] ident[1] ident[0] 00011100 1c 18 12 status 2 r fsc nstd ll nstd mv agc det mv ps det mvcs t3 mvcs det 19 13 status 3 r pal_sw_lock i nterlaced std fld len free_run_act reserved sd_op_50hz gemd inst_hlock 20 14 analog c lamp c ontrol rw cclen 00010010 12 21 15 digital c lamp control 1 rw dct[1] dct[0] dcfe 0000xxxx 00 22 16 reserved 23 17 shaping fi lter c ontrol 1 rw csfm[2] csfm[1] csfm[0] ysfm[4] ysfm[3] ysfm[2] ysfm[1] ysfm[0] 00000001 01 24 18 shaping filter control 2 rw wysfmovr wysfm[4] wysfm[3] wysfm[ 2] wysfm[1] wysfm[0] 10010011 93 25 19 comb f ilter c ontrol rw nsfsel[1] nsfsel[0] psfsel[1] psfsel[0] 11110001 f1 29 1d adi control 2 rw tri_llc en28xtal 01000xxx 40 39 27 pixel delay c ontrol rw swpc auto_pdc_en cta[2] cta[1] cta[0] lta[1] lta[0] 01011000 58 43 2b misc gain c ontrol rw cke pw_upd 11100001 e1 44 2c agc mode c ontrol rw lagc[2] lagc[1] lagc[0] cagc[1] cagc[0] 10101110 ae 45 2d chroma gain control 1 w cagt[1] cagt[0] cmg[11] cmg[10] cmg[9] cmg[8] 11110100 f4 45 2d chroma g ain 1 r cg[11] cg[10] cg[9] cg[8] 46 2e chroma gain control 2 w cmg[7] cmg[6] cmg[5] cmg[4] cmg[3] cmg[2] cmg[1] cmg[0] 00000000 00 46 2e chroma gain 2 r cg[7] cg[6] cg[5] cg[4] cg[3] cg[2] cg[1] cg[0] 47 2f luma gain control 1 w lagt[1] lagt[0] lmg[11] lmg[10] lmg[9] lmg[8] 1111xxxx f0 47 2f luma gain 1 r lg[11] lg[10] lg[9] lg[8] 48 30 luma gain control 2 w lmg[7] lmg[6] lmg[5] lmg[4] lmg[3] lmg[2] lmg[1] lmg[0] xxxxxxxx 00 48 30 luma gain 2 r lg[7] lg [6] lg[5] lg[4] lg[3] lg[2] lg[1] lg[0] 49 31 vs/ field control 1 rw newavmode hvstim 00010010 12 50 32 vs/field control 2 rw vsbho vsbhe 01000001 41 51 33 vs/field control 3 rw vseho vsehe 10000100 84 52 34 hs posi tion control 1 rw hsb[10] hsb[9] hsb[8] hse[10] hse[9] hse[8] 00000000 00 53 35 hs position control 2 rw hsb[7] hsb[6] hsb[5] hsb[4] hsb[3] hsb[2] hsb[1] hsb[0] 00000010 02 54 36 hs position control 3 rw hse[7] hse[6] hse[5] hse[4] hse[3] hse[2] hse[ 1] hse[0] 00000000 00 55 37 polarity rw phs pvs pf pclk 00000001 01 56 38 ntsc comb c ontrol rw ctapsn[1] ctapsn[0] ccmn[2] ccmn[1] ccmn[0] ycmn[2] ycmn[1] ycmn[0] 10000000 80 57 39 pal comb c ontrol rw ctapsp[1] ctapsp[0] ccmp[2] ccmp[1] ccmp[0] ycmp[2] ycmp[1] ycmp[0] 11000000 c0 58 3a adc c ontrol rw pwrdwn_mux_0 pwrdwn_mux_1 pwrdwn_mux_2 mux pdn override 00010000 10 61 3d manual window c ontrol rw ckillthr[2] ckillthr[1] ckillthr[0] 01110010 b2 65 41 resample c ontrol rw sfl_inv 00000001 01 72 48 gemstar control 1 rw gdecel[15] gdecel[14] gdecel[13] gdecel[12] gdecel[11] gdecel[10] gdecel[9] gdecel[8] 00000000 00 73 49 gemstar control 2 rw gdecel[7] gdecel[6] gdecel[5] gdecel[4] gdecel[3] gdecel[2] gdecel[1] gdecel[ 0] 00000000 00 74 4a gemstar control 3 rw gdecol[15] gdecol[14] gdecol[13] gdecol[12] gdecol[11] gdecol[10] gdecol[9] gdecol[8] 00000000 00 75 4b gemstar control 4 rw gdecol[7] gdecol[6] gdecol[5] gdecol[4] gdecol[3] gdecol[2] gdecol[1] gdecol[0] 0000000 0 00 76 4c gemstar control 5 rw gde_sel_old_adf gdecad xxxx0000 00 77 4d cti dnr control 1 rw dnr_en cti_ab[1] cti_ab[0] cti_ab_en cti_en 11101111 ef 78 4e cti dnr control 2 rw cti_c_th[7] cti_c_th[6] cti_c_th[5] cti_c_th[4] cti_c_th[3 ] cti_c_th[2] cti_c_th[1] cti_c_th[0] 00001000 08 80 50 cti dnr control 4 rw dnr_th[7] dnr_th[6] dnr_th[5] dnr_th[4] dnr_th[3] dnr_th[2] dnr_th[1] dnr_th[0] 00001000 08 81 51 lock c ount rw fscle srls col[2] col[1] col[0] cil[2] cil[1] cil[0] 00100100 24 88 58 vs/field pin c ontrol 1 rw adc sampling control vs/field 00000000 00 89 59 general - p u rpose o utputs 2 rw gpo_e nable gpo[3] gpo[2] gpo[1] gpo[0] 00000000 00 143 8f free - run line length 1 w llc_pad_sel[2] llc_pad_ sel[1] llc_pad_ sel[0] 00000000 00 153 99 ccap 1 r ccap1[7] ccap1[6] ccap1[5] ccap1[4] ccap1[3] ccap1[2] ccap1[1] ccap1[0] 154 9a ccap 2 r ccap2[7] ccap2[6] ccap2[5] ccap2[4] ccap2[3] ccap2[2] ccap2[1] ccap2[0]
adv7180 data sheet rev. e | page 80 of 120 address reset dec hex register name rw 7 6 5 4 3 2 1 0 value (hex) 155 9b letterbox 1 r lb_lct[7] lb_lct[6] lb_lct[5] lb_lc t[4] lb_lct[3] lb_lct[2] lb_lct[1] lb_lct[0] 156 9c letterbox 2 r lb_lcm[7] lb_lcm[6] lb_lcm[5] lb_lcm[4] lb_lcm[3] lb_lcm[2] lb_lcm[1] lb_lcm[0] 157 9d letterbox 3 r lb_lcb[7] lb_lcb[6] lb_lcb[5] lb_lcb[4] lb_lcb[3] lb_lcb[2] lb_lcb[1] lb_lcb[0] 178 b2 crc e nable w crc_enable 00011100 1c 195 c3 adc switch 1 rw reserved mux1[2] mux1[1] mux1[0] reserved mux0[2] mux0[1] mux0[0] xxxxxxxx 00 196 c4 adc switch 2 rw man_mux_en reserved mux2[2] mux2[1] mux2[0] 0xxxxxxx 00 220 dc letterbox control 1 rw lb_th[4] lb_th[3] lb_th[2] lb_th[1] lb_th[0] 10101100 ac 221 dd letterbox control 2 rw lb_sl[3] lb_sl[2] lb_sl[1] lb_sl[0] lb_el[3] lb_el[2] lb_el[1] lb_el[0] 01001100 4c 222 de st noise readback 1 r st_noise_vld st_noise[10] s t_noise[9] st_noise[8] 223 df st noise readback 2 r st_noise[7] st_noise[6] st_noise[5] st_noise[4] st_noise[3] st_noise[2] st_noise[1] st_noise[0] 224 e0 reserved 225 e1 sd o ffset cb rw sd_off_c b [7] sd_off_c b [6] sd_off_c b [5] sd_off_c b [4] sd_off_c b [3] sd_off_c b [2] sd_off_c b [1] sd_off_c b [0] 10000000 80 226 e2 sd o ffset cr rw sd_off_c r [7] sd_off_c r [6] sd_off_c r [5] sd_off_cr[ 4] sd_off_c r [3] sd_off_c r [2] sd_off_c r [1] sd_off_c r [0] 10000000 80 227 e3 sd s aturation cb rw sd_sat_c b [7] sd_sat_c b[ 6] sd_sat_c b [5] sd_sat_c b [4] sd_sat_c b [3] sd_sat_c b [2] sd_sat_c b [1] sd_sat_c b [0] 10000000 80 228 e4 sd s aturation cr rw sd_sat_c r [7] sd_sat_c r [6] sd_sat_c r [5] sd_sat_c r [4] sd_sat_c r [3] sd_sat_c r [2] sd_sat_c r [1] sd_sat_c r [0] 10000000 80 229 e5 ntsc v b it b egin rw nvbegdelo nvbegdele nvbegsign nvbeg[4] nvbeg[3] nvbeg[2] nvbeg[1] nvbeg[0] 00100101 25 230 e6 ntsc v b it e nd rw nvenddelo nvenddele nvendsign nvend[4] nvend[3] nvend[2] nvend[1] nvend[0] 00000100 04 231 e7 ntsc f bit t oggle rw nftogdelo nftogdel e nftogsign nftog[4] nftog[3] nftog[2] nftog[1] nftog[0] 01100011 63 232 e8 pal v b it b egin rw pvbegdelo pvbegdele pvbegsign pvbeg[4] pvbeg[3] pvbeg[2] pvbeg[1] pvbeg[0] 01100101 65 233 e9 pal v b it e nd rw pvenddelo pvenddele pvendsign pvend[4] pvend[3] pvend[2] pvend[1] pvend[0] 00010100 14 234 ea pal f b it t oggle rw pftogdelo pftogdele pftogsign pftog[4] pftog[3] pftog[2] pftog[1] pftog[0] 01100011 63 235 eb vblank control 1 rw nvbiolcm[1] nvbiolcm[0] nvbielcm[1] nvbielcm[0] pvbiolcm[1] pvbiolcm[0] pv bielcm[1] pvbielcm[0] 01010101 55 236 ec vblank control 2 rw nvbioccm[1] nvbioccm[0] nvbieccm[1] nvbieccm[0] pvbioccm[1] pvbioccm[0] pvbieccm[1] pvbieccm[0] 01010101 55 243 f3 afe_control 1 rw aa_filt_ man_ovr aa_filt_en[2] aa_filt_en[1] aa_filt_en[0 ] 00000000 00 244 f4 drive s trength rw dr_str[1] dr_str[0] dr_str_c[1] dr_str_c[0] dr_str_s[1] dr_str_s[0] xx010101 15 248 f8 if c omp c ontrol rw iffiltsel[2] iffiltsel[1] iffiltsel[0] 00000000 00 249 f9 vs mode c ontrol rw vs_coast_ mode[1] vs_coast_ mode[0] extend_vs_ min_freq extend_vs_ max_freq 00000011 03 251 fb peaking c ontrol rw peaking_ gain[7] peaking_ gain[6] peaking_ gain[5] peaking_ gain[4] peaking_ gain[3] peaking_ gain[2] peaking_ gain[1] peaking_ gain[0] 01000000 40 2 52 fc coring t hreshold rw dnr_th2[7] dnr_th2[6] dnr_th2[5] dnr_th2[4] dnr_th2[3] dnr_th2[2] dnr_th2[1] dnr_th2[0] 00000100 04 1 this feature applies to the 48 - lead , 40 - lead, and 32 - lead lfcsp only because vs or field is shared on a single pin. 2 this feature applies to the 64 - lead and 48 - lead lqfp only.
data sheet adv7180 rev. g | page 81 of 120 table 106 . interrupt system register map details 1, 2 address register name rw 7 6 5 4 3 2 1 0 reset value (hex) dec hex 64 40 interrupt configuration 1 rw intrq_dur_ sel[1] intrq_dur_ sel[0] mv_intrq_ sel[1] mv_intrq_ sel[0] mpu_stim_ intrq intrq_op_ sel[1] intrq_op_sel[0] 0001x000 10 66 42 interrupt status 1 r mv_ps_cs_q sd_fr_chng_ q sd_unlock_q sd_lock_q 67 43 interrupt clear 1 w mv_ps_cs_clr sd_fr_chng_ clr sd_unlock_ clr sd_lock_clr x0000000 00 68 44 interrupt mask 1 rw mv_ps_cs_ mskb sd_fr_chng_ mskb sd_unlock_ mskb sd_lock_mskb x0000000 00 69 45 raw status 1 r mpu_stim_ intrq even_field ccapd 70 46 interrupt status 2 r mpu_stim_ intrq_q s d_field_ chngd_q gemd_q ccapd_q 71 47 interrupt clear 2 w mpu_stim_ intrq_clr s d_field_ chngd_clr gemd_clr ccapd_clr 0xx00000 00 72 48 interru pt mask 2 rw mpu_stim_ intrq_mskb sd _field_ chngd_mskb gemd_mskb ccapd_mskb 0xx00000 00 73 49 raw status 2 r scm_lock sd_h_lock sd_v_lock sd_op_50hz 74 4a interrupt status 3 r pal_sw_lk_ chng_q scm_lock_ chng_q sd_ad_chng_q sd_h_loc k_ chng_q sd_v_lock_ chng_q sd_op_chng_q 75 4b interrupt clear 3 w pal_sw_lk_ chng_clr scm_lock_ chng_clr sd_ad_chng_ clr sd_h_lock_ chng_clr sd_v_lock_ chng_clr sd_op_chng_ clr xx000000 00 76 4c interrupt mask 3 rw pal_sw_lk_ chng_mskb scm_l ock_ chng_mskb sd_ad_chng_ mskb sd_h_lock_ chng_mskb sd_v_lock_ chng_mskb sd_op_chng_ mskb xx000000 00 78 4e interrupt status 4 r vdp_vitc_q vdp_gs_vps_ pdc_utc_ chng_q vdp_cgms_ wss_chngd_q vdp_ccapd_q 79 4f interrupt clear 4 w vdp_vitc_cl r vdp_gs_vps_ pdc_utc_ chng_clr vdp_cgms_ wss_chngd_ clr vdp_ccapd_clr 00x0x0x0 00 80 50 interrupt mask 4 rw vdp_vitc_mskb vdp_gs_vps_ pdc_utc_ chng_mskb vdp_cgms_ wss_chngd_ mskb vdp_ccapd_ mskb 00x0x0x0 00 96 60 vdp_config_1 rw w st_pkt_ decode_ disable vdp_ttxt_ type_man_ enable vdp_ttxt_ type_man[1] vdp_ttxt_ type_man[ 0] 10001000 88 97 61 vdp_config_2 rw auto_detect_ gs_type 0001xx00 10 98 62 vdp_adf_config_1 rw adf_enable adf_mode[1] adf_mode[0] adf_did[4] adf _did[3] adf_did[2] adf_did[1] adf_did[0] 00010101 15 99 63 vdp_adf_ config_2 rw duplicate_adf adf_sdid[5] adf_sdid[4] adf_sdid[3] adf_sdid[2] adf_sdid[1] adf_sdid[0] 0x101010 2a 100 64 vdp_line_00e rw man_line_pgm vbi_data_ p318[3] vbi_data_ p318[2] vbi_data_ p318[1] vbi_data_ p318[0] 0xxx0000 00 101 65 vdp_line_00f rw vbi_data_ p6_n23[3] vbi_data_ p6_n23[2] vbi_data_ p6_n23[1] vbi_data_ p6_n23[0] vbi_data_ p319_n286[3] vbi_data_ p319_n286[2] vbi_data_ p319_n286[1] vbi_data_ p319_n286[0] 00000000 00 102 66 vdp_line_010 rw vbi_data_ p7_n24[3] vbi_data_ p7_n24[2] vbi_data_ p7_n24[1] vbi_data_ p7_n24[0] vbi_data_ p320_n287[3] vbi_data_ p320_n287[2] vbi_data_ p320_n287[1] vbi_data_ p320_n287[0] 00000000 00 103 67 vdp_line_011 rw vbi_data_ p8_n25 [3] vbi_data_ p8_n25[2] vbi_data_ p8_n25[1] vbi_data_ p8_n25[0] vbi_data_ p321_n288[3] vbi_data_ p321_n288[2] vbi_data_ p321_n288[1] vbi_data_ p321_n288[0] 00000000 00 104 68 vdp_line_012 rw vbi_data_ p9[3] vbi_data_ p9[2] vbi_data_ p9[1] vbi_data_ p9[0] vbi_data_ p322[3] vbi_data_ p322[2] vbi_data_ p322[1] vbi_data_ p322[0] 00000000 00 105 69 vdp_line_013 rw vbi_data_ p10[3] vbi_data_ p10[2] vbi_data_ p10[1] vbi_data_ p10[0] vbi_data_ p323[3] vbi_data_ p323[2] vbi_data_ p323[1] vbi_data_ p323[0] 00000000 00 106 6a vdp_line_014 rw vbi_data_ p11[3] vbi_data_ p11[2] vbi_data_ p11[1] vbi_data_ p11[0] vbi_data_ p324_n272[3] vbi_data_ p324_n272[2] vbi_data_ p324_n272[1] vbi_data_ p324_n272[0] 00000000 00 107 6b vdp_line_015 rw vbi_data_ p12_n10[3] vbi_dat a_ p12_n10[2] vbi_data_ p12_n10[1] vbi_data_ p12_n10[0] vbi_data_ p325_n273[3] vbi_data_ p325_n273[2] vbi_data_ p325_n273[1] vbi_data_ p325_n273[0] 00000000 00 108 6c vdp_line_016 rw vbi_data_ p13_n11[3] vbi_data_ p13_n11[2] vbi_data_ p13_n11[1] vbi_data _ p13_n11[0] vbi_data_ p326_n274[3] vbi_data_ p326_n274[2] vbi_data_ p326_n274[1] vbi_data_ p326_n274[0] 00000000 00 109 6d vdp_line_017 rw vbi_data_ p14_n12[3] vbi_data_ p14_n12[2] vbi_data_ p14_n12[1] vbi_data_ p14_n12[0] vbi_data_ p327_n275[3] vbi_dat a_ p327_n275[2] vbi_data_ p327_n275[1] vbi_data_ p327_n275[0] 00000000 00 110 6e vdp_line_018 rw vbi_data_ p15_n13[3] vbi_data_ p15_n13[2] vbi_data_ p15_n13[1] vbi_data_ p15_n13[0] vbi_data_ p328_n276[3] vbi_data_ p328_n276[2] vbi_data_ p328_n276[1] vbi_ data_ p328_n276[0] 00000000 00 111 6f vdp_line_019 rw vbi_data_ p16_n14[3] vbi_data_ p16_n14[2] vbi_data_ p16_n14[1] vbi_data_ p16_n14[0] vbi_data_ p329_n277[3] vbi_data_ p329_n277[2] vbi_data_ p329_n277[1] vbi_data_ p329_n277[0] 00000000 00 112 70 vdp _line_01a rw vbi_data_ p17_n15[3] vbi_data_ p17_n15[2] vbi_data_ p17_n15[1] vbi_data_ p17_n15[0] vbi_data_ p330_n278[3] vbi_data_ p330_n278[2] vbi_data_ p330_n278[1] vbi_data_ p330_n278[0] 00000000 00 113 71 vdp_line_01b rw vbi_data_ p18_n16[3] vbi_data _ p18_n16[2] vbi_data_ p18_n16[1] vbi_data_ p18_n16[0] vbi_data_ p331_n279[3] vbi_data_ p331_n279[2] vbi_data_ p331_n279[1] vbi_data_ p331_n279[0] 00000000 00 114 72 vdp_line_01c rw vbi_data_ p19_n17[3] vbi_data_ p19_n17[2] vbi_data_ p19_n17[1] vbi_data_ p19_n17[0] vbi_data_ p332_n280[3] vbi_data_ p332_n280[2] vbi_data_ p332_n280[1] vbi_data_ p332_n280[0] 00000000 00 115 73 vdp_line_01d rw vbi_data_ p20_n18[3] vbi_data_ p20_n18[2] vbi_data_ p20_n18[1] vbi_data_ p20_n18[0] vbi_data_ p333_n281[3] vbi_data _ p333_n281[2] vbi_data_ p333_n281[1] vbi_data_ p333_n281[0] 00000000 00 116 74 vdp_line_01e rw vbi_data_ p21_n19[3] vbi_data_ p21_n19[2] vbi_data_ p21_n19[1] vbi_data_ p21_n19[0] vbi_data_ p334_n282[3] vbi_data_ p334_n282[2] vbi_data_ p334_n282[1] vbi_d ata_ p334_n282[0] 00000000 00 117 75 vdp_line_01f rw vbi_data_ p22_n20[3] vbi_data_ p22_n20[2] vbi_data_ p22_n20[1] vbi_data_ p22_n20[0] vbi_data_ p335_n283[3] vbi_data_ p335_n283[2] vbi_data_ p335_n283[1] vbi_data_ p335_n283[0] 00000000 00
adv7180 data sheet rev. g | page 82 of 120 address register name rw 7 6 5 4 3 2 1 0 reset value (hex) dec hex 118 76 vdp_ line_020 rw vbi_data_ p23_n21[3] vbi_data_ p23_n21[2] vbi_data_ p23_n21[1] vbi_data_ p23_n21[0] vbi_data_ p336_n284[3] vbi_data_ p336_n284[2] vbi_data_ p336_n284[1] vbi_data_ p336_n284[0] 00000000 00 119 77 vdp_line_021 rw vbi_data_ p24_n22[3] vbi_data_ p24_n22[2] vbi_data_ p24_n22[1] vbi_data_ p24_n22[0] vbi_data_ p337_n285[3] vbi_data_ p337_n285[2] vbi_data_ p337_n285[1] vbi_data_ p337_n285[0] 00000000 00 120 78 vdp_status r ttxt_avl vitc_avl gs_data_ type gs_pdc_vps_ utc_avl cgms_wss_avl cc_even_fi eld cc_avl 120 78 vdp_status_ clear w vitc_clear gs_pdc_vps_ utc_clear cgms_wss_ clear cc_clear 00000000 00 121 79 vdp_ccap_ data_0 r ccap_byte_1 [7] ccap_byte_1[6] ccap_byte_1[5] ccap_byte_1[4] ccap_byte_1[3] ccap_byte_1[2] ccap_byte_1[1] ccap_byt e_1[0] 122 7a vdp_ccap_ data_1 r ccap_byte_2[7] ccap_byte_2[6] ccap_byte_2[5] ccap_byte_2[4] ccap_byte_2[3] ccap_byte_2[2] ccap_byte_2[1] ccap_byte_2[0] 125 7d vdp_cgms_ wss_data_0 r cgms_crc[5] cgms_crc[4] cgms_crc[3] cgms_crc[2] 126 7e vd p_cgms_ wss_data_1 r cgms_crc[1] cgms_crc[0] cgms_wss[13] cgms_wss[12] cgms_wss[11] cgms_wss[10] cgms_wss[9] cgms_wss[8] 127 7f vdp_cgms_ wss_data_2 r cgms_wss[7] cgms_wss[6] cgms_wss[5] cgms_wss[4] cgms_wss[3] cgms_wss[2] cgms_wss[1] cgms_wss[0] 1 32 84 vdp_gs_vps_ pdc_utc_0 r gs_vps_pdc_ utc_byte_0[7] gs_vps_pdc_ utc_byte_0[6] gs_vps_pdc_ utc_byte_0[5] gs_vps_pdc_ utc_byte_0[4] gs_vps_pdc_ utc_byte_0[3] gs_vps_pdc_ utc_byte_0[2] gs_vps_pdc_ utc_byte_0[1] gs_vps_pdc_ utc_byte_0[0] 133 85 vdp_gs _vps_ pdc_utc_1 r gs_vps_pdc_ utc_byte_1[7] gs_vps_pdc_ utc_byte_1[6] gs_vps_pdc_ utc_byte_1[5] gs_vps_pdc_ utc_byte_1[4] gs_vps_pdc_ utc_byte_1[3] gs_vps_pdc_ utc_byte_1[2] gs_vps_pdc_ utc_byte_1[1] gs_vps_pdc_ utc_byte_1[0] 134 86 vdp_gs_vps_ pdc_utc _2 r gs_vps_pdc_ utc_byte_2[7] gs_vps_pdc_ utc_byte_2[6] gs_vps_pdc_ utc_byte_2[5] gs_vps_pdc_ utc_byte_2[4] gs_vps_pdc_ utc_byte_2[3] gs_vps_pdc_ utc_byte_2[2] gs_vps_pdc_ utc_byte_2[1] gs_vps_pdc_ utc_byte_2[0] 135 87 vdp_gs_vps_ pdc_utc_3 r gs_vps_p dc_ utc_byte_3[7] gs_vps_pdc_ utc_byte_3[6] gs_vps_pdc_ utc_byte_3[5] gs_vps_pdc_ utc_byte_3[4] gs_vps_pdc_ utc_byte_3[3] gs_vps_pdc_ utc_byte_3[2] gs_vps_pdc_ utc_byte_3[1] gs_vps_pdc_ utc_byte_3[0] 136 88 vdp_vps_ pdc_utc_4 r vps_pdc_utc_ byte_4[7] v ps_pdc_utc_ byte_4[6] vps_pdc_utc_ byte_4[5] vps_pdc_utc_ byte_4[4] vps_pdc_utc_ byte_4[3] vps_pdc_utc_ byte_4[2] vps_pdc_utc_ byte_4[1] vps_pdc_utc_ byte_4[0] 137 89 vdp_vps_ pdc_utc_5 r vps_pdc_utc_ byte_5[7] vps_pdc_utc_ byte_5[6] vps_pdc_utc_ byte_ 5[5] vps_pdc_utc_ byte_5[4] vps_pdc_utc_ byte_5[3] vps_pdc_utc_ byte_5[2] vps_pdc_utc_ byte_5[1] vps_pdc_utc_ byte_5[0] 138 8a vdp_vps_ pdc_utc_6 r vps_pdc_utc_ byte_6[7] vps_pdc_utc_ byte_6[6] vps_pdc_utc_ byte_6[5] vps_pdc_utc_ byte_6[4] vps_pdc_utc_ byte_6[3] vps_pdc_utc_ byte_6[2] vps_pdc_utc_ byte_6[1] vps_pdc_utc_ byte_6[0] 139 8b vdp_vps_pdc_ utc_7 r vps_pdc_utc_ byte_7[7] vps_pdc_utc_ byte_7[6] vps_pdc_utc_ byte_7[5] vps_pdc_utc_ byte_7[4] vps_pdc_utc_ byte_7[3] vps_pdc_utc_ byte_7[2] vps_pd c_utc_ byte_7[1] vps_pdc_utc_ byte_7[0] 140 8c vdp_vps_pdc_ utc_8 r vps_pdc_utc_ byte_8[7] vps_pdc_utc_ byte_8[6] vps_pdc_utc_ byte_8[5] vps_pdc_utc_ byte_8[4] vps_pdc_utc_ byte_8[3] vps_pdc_utc_ byte_8[2] vps_pdc_utc_ byte_8[1] vps_pdc_utc_ byte_8[0] 141 8d vdp_vps_pdc_ utc_9 r vps_pdc_utc_ byte_9[7] vps_pdc_utc_ byte_9[6] vps_pdc_utc_ byte_9[5] vps_pdc_utc_ byte_9[4] vps_pdc_utc_ byte_9[3] vps_pdc_utc_ byte_9[2] vps_pdc_utc_ byte_9[1] vps_pdc_utc_ byte_9[0] 142 8e vdp_vps_pdc_ utc_10 r vps_pdc _utc_ byte_10[7] vps_pdc_utc_ byte_10[6] vps_pdc_utc_ byte_10[5] vps_pdc_utc_ byte_10[4] vps_pdc_utc_ byte_10[3] vps_pdc_utc_ byte_10[2] vps_pdc_utc_ byte_10[1] vps_pdc_utc_ byte_10[0] 143 8f vdp_vps_pdc_ utc_11 r vps_pdc_utc_ byte_11[7] vps_pdc_utc_ b yte_11[6] vps_pdc_utc_ byte_11[5] vps_pdc_utc_ byte_11[4] vps_pdc_utc_ byte_11[3] vps_pdc_utc_ byte_11[2] vps_pdc_utc_ byte_11[1] vps_pdc_utc_ byte_11[0] 144 90 vdp_vps_pdc_ utc_12 r vps_pdc_utc_ byte_12[7] vps_pdc_utc_ byte_12[6] vps_pdc_utc_ byte_12[ 5] vps_pdc_utc_ byte_12[4] vps_pdc_utc_ byte_12[3] vps_pdc_utc_ byte_12[2] vps_pdc_utc_ byte_12[1] vps_pdc_utc_ byte_12[0] 146 92 vdp_vitc_data_0 r vitc_data_0[7] vitc_data_0[6] vitc_data_0[5] vitc_data_0[4] vitc_data_0[3] vitc_data_0[2] vitc_data_0[1] vitc_data_0[0] 147 93 vdp_vitc_data_1 r vitc_data_1[7] vitc_data_1[6] vitc_data_1[5] vitc_data_1[4] vitc_data_1[3] vitc_data_1[2] vitc_data_1[1] vitc_data_1[0] 148 94 vdp_vitc_data_2 r vitc_data_2[7] vitc_data_2[6] vitc_data_2[5] vitc_data_2[4] vi tc_data_2[3] vitc_data_2[2] vitc_data_2[1] vitc_data_2[0] 149 95 vdp_vitc_data_3 r vitc_data_3[7] vitc_data_3[6] vitc_data_3[5] vitc_data_3[4] vitc_data_3[3] vitc_data_3[2] vitc_data_3[1] vitc_data_3[0] 150 96 vdp_vitc_data_4 r vitc_data_4[7] vitc_ data_4[6] vitc_data_4[5] vitc_data_4[4] vitc_data_4[3] vitc_data_4[2] vitc_data_4[1] vitc_data_4[0] 151 97 vdp_vitc_data_5 r vitc_data_5[7] vitc_data_5[6] vitc_data_5[5] vitc_data_5[4] vitc_data_5[3] vitc_data_5[2] vitc_data_5[1] vitc_data_5[0] 152 98 vdp_vitc_data_6 r vitc_data_6[7] vitc_data_6[6] vitc_data_6[5] vitc_data_6[4] vitc_data_6[3] vitc_data_6[2] vitc_data_6[1] vitc_data_6[0] 153 99 vdp_vitc_data_7 r vitc_data_7[7] vitc_data_7[6] vitc_data_7[5] vitc_data_7[4] vitc_data_7[3] vitc_data_ 7[2] vitc_data_7[1] vitc_data_7[0] 154 9a vdp_vitc_data_8 r vitc_data_8[7] vitc_data_8[6] vitc_data_8[5] vitc_data_8[4] vitc_data_8[3] vitc_data_8[2] vitc_data_8[1] vitc_data_8[0] 155 9b vdp_vitc_calc_ crc r vitc_crc[7] vitc_crc[6] vitc_crc[5] vitc _crc[4] vitc_crc[3] vitc_crc[2] vitc_crc[1] vitc_crc[0] 156 9c vdp_output_sel rw i 2 c_gs_vps_ pdc_utc[1] i 2 c_gs_vps_ pdc_utc[0] gs_vps_ pdc_utc_ cb_change wss_cgms_ cb_change 00110000 30 1 to access the registers listed in table 10 6 , sub_u sr_en in register ad dress 0x0e must be programmed to 1. 2 x in a reset value indicates do not care.
data sheet adv7180 rev. g | page 83 of 120 table 107 . register map desc riptions (normal operation) 1, 2 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x00 input control insel[3:0]; the insel bits allow the user to select an input channel and the input form at; r efer to table 13 and table 14 f or full routing details 0 0 0 0 composite (lqfp and lfcsp) mandat ory write required for y/c (s -v ideo mode) reg 0x58 = 0x04; se e reg 0x58 for bit description 0 0 0 1 composite (lqfp)/reserved (lfcsp) 0 0 1 0 composite (lqfp)/reserved (lfcsp) 0 0 1 1 composite (lqfp and lfcsp) 0 1 0 0 composite (lqfp and lfcsp) 0 1 0 1 composite (lqfp)/r eserved (lfcsp) 0 1 1 0 s- video (lqfp and lfcsp) 0 1 1 1 s- video (lqfp)/reserved (lfcsp) 1 0 0 0 s- video (lqfp)/reserved (lfcsp) 1 0 0 1 yprpb (lqfp and lfcsp) 1 0 1 0 yprpb (lqfp)/reserved (lfcsp) 1 0 1 1 reserved (lqfp and lfcsp) 1 1 0 0 reserved (lqfp and lfcsp) 1 1 0 1 reserved (lqfp and lfcsp) 1 1 1 0 reserved (lqfp and lfcsp) 1 1 1 1 reserved (lqfp and lfcsp) vid_sel[3:0]; the vid_sel bits allow the user to select the input video standard 0 0 0 0 autodetect pal b/g/h/i/d,ntsc j (no pedestal), secam 0 0 0 1 autodetect pal b/g/h/i/d, ntsc m (pedestal), secam 0 0 1 0 autodetect ( pal n) (pedestal), ntsc j (no pedestal), secam 0 0 1 1 autodetect (pal n) (pedestal), ntsc m (pedestal), secam 0 1 0 0 ntsc j 0 1 0 1 ntsc m 0 1 1 0 pal 60 0 1 1 1 ntsc 4.43 1 0 0 0 pal b/g/h/i/d 1 0 0 1 pal n = pal b/g/h/i/d (with pedestal) 1 0 1 0 pal m (without pedestal) 1 0 1 1 pal m 1 1 0 0 pal combination n 1 1 0 1 pal combination n (with pedestal) 1 1 1 0 secam 1 1 1 1 secam (with pedestal)
adv7180 data sheet rev. g | page 84 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x01 video s election reserved 0 0 set to defau lt sqpe 0 disable square pixel mode 1 enable square pixel mode envsproc 0 disable vsync processor 1 enable vsync processor reserved 0 set to default betacam 0 standard video input 1 betacam input enable enhspll 0 disable hsync processor 1 enable hsync processor reserved 1 set to default 0x03 output c ontrol sd_dup_av; duplicates the av codes from the luma into the chroma path 0 a v codes to suit 8 - bit interleaved data output 1 av codes duplicated (for 16 - bit interfaces) reserved 0 set as default of_sel[3:0]; allows the user to choose from a set of output formats 0 0 0 0 reserved 0 0 0 1 reser ved 0 0 1 0 16- bit at llc 4:2:2 options apply to 64- lead lqfp only 0 0 1 1 8- bit at llc 4:2:2 itu - r bt.656 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved tod; three - state output drivers; this bit allows the user to three - st ate the output drivers ; pixel outputs , hs, vs, field, and sfl 0 output pins enabled see also tim_oe and tri_llc 1 drivers three - stated vbi_en; allows vbi data (line 1 to line 21) to be passed through with only a minimum amount of filtering performed 0 all lines filtered and scaled 1 only active video region filtered 0x04 extended o utput c ontrol range; allows the user to select the range of output values; can be itu - r bt.656 compliant or can fill the whol e accessible number range 0 16 y 235, 16 c/p 240 itu - r bt.656 1 1 y 254, 1 c/p 254 extended range en_sfl_pin 0 sfl output is disabled sfl output enables encoder and decoder to be connected directly 1 sfl information output on the sfl pin bl_c_vbi; blank chroma during vbi; if set, it enables data in the vbi region to be passed through the decoder undistorted 0 decode and output color during vbi 1 blank cr and cb tim_oe; timi ng signals output enable 0 hs, vs, field three - stated controlled by tod 1 hs, vs, field forced active
data sheet adv7180 rev. g | page 85 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 reserved x x reserved 1 bt.656 - 4; allows the user to select an output mode compatible with itu - r bt.656 - 3/ -4 0 itu - r bt.656 - 3 compatible 1 itu - r bt.656 - 4 compatible 0x07 autodetect e nable ad_pal_en; pal b/d/i/g/h autodetect enable 0 disable 1 enable ad_ntsc_en; ntsc autodetect enable 0 disable 1 enable ad_palm_en; pal m autodetect enable 0 disable 1 enable ad_paln_en; pal n autodetect enable 0 disable 1 enable ad_p60_en; pal 60 autodetect enable 0 disable 1 enable ad_n443_en; ntsc 4.43 autodetect enable 0 disable 1 enable ad_secam_en; secam autodetect enable 0 disable 1 enable ad_sec525_ en; secam 525 autodetect enable 0 disable 1 enable 0x08 contrast con[7:0]; contrast adjust; this is the user control for contrast adjustment 1 0 0 0 0 0 0 0 luma gain = 1 0x00 gain = 0, 0x80 gain = 1, 0xff gain = 2 0x0a brightness bri[7:0]; this register controls the brightness of the video signal 0 0 0 0 0 0 0 0 0x00 = 0 ire, 0x7f = +30 ire, 0x80 = ?30 ire 0x0b hue hue[7:0]; this register contains the value for the color hue adjustment 0 0 0 0 0 0 0 0 hue range = ?90 to +90 0x0c default value y def_val_en; default value enable 0 free - run mode dependent on def_val_auto_en 1 force free - run mode on and output blue screen def_val_auto_en; default value automatic enable 0 disable fr ee - run mode when lock is lost, free - run mode can be enabled to output stable timing, clock, and a set color 1 enable automatic free - run mode (blue screen) def_y[5:0]; default v alue is y; this register holds the y default value 0 0 1 1 0 1 y[7:0] = {def_y[5:0], 0, 0} default y value output in free - run mode 0x0d default value c def_c[7:0]; default value is c; the cr and cb default values are defined in this register 0 1 1 1 1 1 0 0 cr[ 3 :0] = {def_c[7:4], 0, 0, 0, 0} cb [3 :0] = {def_c[3:0], 0, 0, 0, 0} default cb/cr value output in free - run mode; default values give blue screen output
adv7180 data sheet rev. g | page 86 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x0e adi control 1 reserved 0 0 0 0 0 set as default sub_usr_en; enables user to access the interrupt/ vdp registe r map 0 access main register space see figure 53 1 access interrupt/vdp register space reserved 0 0 set as default 0x0f power m anagement reserved 0 0 set to default pd bp; power - down bit priority selects between pwrdwn bit or pin control 0 chip power - down controlled by pin not applicable for 32 -l ead lfcsp 1 bit has priority (pin disregarded) reserved 0 0 set to default pwrdwn; power - down p laces the decoder into a full power - down mode 0 system functional 1 powered down see pdbp, 0x0f bit 2 reserved 0 set to default reset; chip reset, loads all i 2 c bits with default values 0 normal operation 1 start reset sequence executing reset takes approx i- mately 2 ms; this bit is self - clearing 0x10 status 1 (r ead o nly) in_lock x 1 = in lock (now) provides info about the internal status of the decoder lost_lock x 1 = lost lock (sinc e last read) fsc_lock x 1 = f sc lock (now) follow_pw x 1 = peak white agc mode active ad_result[2:0]; auto - detection result reports the standard of the input video 0 0 0 ntsc m/j detected standard 0 0 1 ntsc 4. 43 0 1 0 pal m 0 1 1 pal 60 1 0 0 pal b/g/h/i/d 1 0 1 secam 1 1 0 pal combination n 1 1 1 secam 525 col_kill x 1 = color kill is active color kill 0x11 ident (r ead o nly) ident[7:0]; p rovides identification on the revision of the part 0 0 0 1 1 1 0 0 power - up value = 0x1c 0x12 status 2 (r ead o nly) mvcs det x mv color striping detected 1 = detected mvcs t3 x mv color striping type 0 = type 2 , 1 = type 3 mv ps det x mv pseudosync detected 1 = detected mv agc det x mv agc pulses detected 1 = detected ll nstd x nonstandard line length 1 = detected fsc nstd x f sc frequency nonstandard 1 = detected reserved x x 0x13 statu s 3 (r ead o nly) inst_hlock x 1 = horizontal lock achieved unfiltered gemd x 1 = gemstar data detected sd_op_50hz 0 sd 60 hz detected sd field rate detect 1 sd 50 hz detected reserved x free_run_act x 1 = free - run mode active blue screen output std fld len x 1 = field length standard correct field length found i nterlaced x 1 = interlaced video detected field sequence found pal_sw_lock x 1 = swinging burst detected re liable swinging burst sequence
data sheet adv7180 rev. g | page 87 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x14 analog clamp c ontrol reserved 0 0 1 0 set to default cclen; current clamp enable allows the user to switch off the current sources in the analog front 0 current sources switched off 1 curren t sources enabled reserved 0 0 0 set to default 0x15 digital clamp control 1 reserved x x x x set to default dcfe; digital clamp freeze enable 0 digital clamp on 1 digital clamp off dct[1:0]; digital clamp timing determines the time constant of the digital fine clamp circuitry 0 0 slow (tc = 1 sec) 0 1 medium (tc = 0.5 sec) 1 0 fast (tc = 0.1 sec) 1 1 tc dependent on video reserved 0 set to default 0x17 shaping f ilter control 1 ysfm[4:0]; selects y shaping filter mode in cvbs - only mode; allows the user to select a wide range of low - pass and notch filters; if either auto mode is selected, the decoder selects the optimum y filter depending on the cvbs video sourc e quality (good vs. poor) 0 0 0 0 0 auto wide notch f or poor quality sources or wide band filter with comb for good quality input decoder selects optimum y shaping filter depending on cvbs quality 0 0 0 0 1 auto narrow notch for poor quality source s or wideband filter with comb for good quality input 0 0 0 1 0 svhs 1 if one of these modes is selected, the decoder does not change filter modes; depending on video quality, a fixed filter response (the one selected) is used for good and b ad quality video 0 0 0 1 1 svhs 2 0 0 1 0 0 svhs 3 0 0 1 0 1 svhs 4 0 0 1 1 0 svhs 5 0 0 1 1 1 svhs 6 0 1 0 0 0 svhs 7 0 1 0 0 1 svhs 8 0 1 0 1 0 svhs 9 0 1 0 1 1 svhs 10 0 1 1 0 0 svhs 11 0 1 1 0 1 svhs 12 0 1 1 1 0 svhs 13 0 1 1 1 1 svhs 14 1 0 0 0 0 svhs 15 1 0 0 0 1 svhs 16 1 0 0 1 0 svhs 17 1 0 0 1 1 svhs 18 (ccir 601) 1 0 1 0 0 pal nn1 1 0 1 0 1 pal nn2 1 0 1 1 0 pal nn3 1 0 1 1 1 pal wn1 1 1 0 0 0 pal wn2 1 1 0 0 1 ntsc nn1 1 1 0 1 0 ntsc nn2 1 1 0 1 1 ntsc nn3 1 1 1 0 0 ntsc wn1 1 1 1 0 1 ntsc wn2 1 1 1 1 0 ntsc wn3 1 1 1 1 1 reserved csfm[2:0]; c shaping filter mode allows selection from a range of low - pass chrominance filters; if either auto mode is selected, the decoder selects the optimum c filter depending on the cvbs video source quality ( good vs. bad); nonauto settings force a c filter for all standards and quality of cvbs video 0 0 0 auto selection 1.5 mhz automatically selects a c filter based on video standard and quality 0 0 1 auto selection 2.17 mhz 0 1 0 sh 1 selects a c filter for all video standards and for good and bad video 0 1 1 sh2 1 0 0 sh3 1 0 1 sh4 1 1 0 sh5 1 1 1 wideband mode
adv7180 data sheet rev. g | page 88 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x18 shaping filter control 2 wysfm[4:0]; wideband y shaping filter mod e allows the user to select which y shaping filter is used for the y component of y/c, yprpb, b/w input signals; it is also used when a good quality input cvbs signal is detected; for all other inputs, the y shaping filter chosen is controlled by ysfm[4: 0] 0 0 0 0 0 reserved, do not use 0 0 0 0 1 reserved, do not use 0 0 0 1 0 svhs 1 0 0 0 1 1 svhs 2 0 0 1 0 0 svhs 3 0 0 1 0 1 svhs 4 0 0 1 1 0 svhs 5 0 0 1 1 1 svhs 6 0 1 0 0 0 svhs 7 0 1 0 0 1 svhs 8 0 1 0 1 0 svhs 9 0 1 0 1 1 svhs 10 0 1 1 0 0 svhs 11 0 1 1 0 1 svhs 12 0 1 1 1 0 svhs 13 0 1 1 1 1 svhs 14 1 0 0 0 0 svhs 15 1 0 0 0 1 svhs 16 1 0 0 1 0 svhs 17 1 0 0 1 1 svhs 18 (ccir 601) 1 0 1 0 0 reserved, do not use ~ ~ ~ ~ ~ reserved, do not use 1 1 1 1 1 reserved, do not use reserved 0 0 set to default wysfmovr; enables use of the automatic wysf m filter 0 autoselection of best filter 1 manual select filter using wysfm[4:0] 0x19 comb filter c ontrol psfsel[1:0]; controls the signal bandwidth that is fed to the comb filters (pal) 0 0 narrow 0 1 medium 1 0 wide 1 1 widest nsfsel[1:0]; controls the signal bandwidth that is fed to the comb filters (ntsc) 0 0 narrow 0 1 medium 1 0 medium 1 1 wide reserved 1 1 1 1 set as default 0x1d adi co ntrol 2 reserved 0 0 0 x x x set to default en28xtal 0 reserved, do not use 1 use 28 mhz crystal tri_llc 0 llc pin active 1 llc pin three - stated
data sheet adv7180 rev. g | page 89 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x27 pixel delay c ontrol lta[1:0]; luma timing adjust allow s the user to speci fy a timing differ ence between chroma and luma samples 0 0 no delay cvbs mode lta[1:0] = 00b, s-v ideo mode lta[1:0] = 01b, yprpb mode lta[1:0] = 01b 0 1 luma one clock (37 ns) late 1 0 luma two clocks (74 n s) early 1 1 luma one clock (37 ns) early reserved 0 set to 0 cta[2:0]; c hroma timing adjust allows a specified timing difference between the luma and chroma samples 0 0 0 not a valid setting cvbs mode cta[2:0] = 011b, s- video mode cta[2:0] = 101b, yprpb mode cta[2:0] = 110b 0 0 1 chroma + two pixels (early) 0 1 0 chroma + one pixel (early) 0 1 1 no delay 1 0 0 chroma ? one pixel (late) 1 0 1 chroma ? two pixels (late) 1 1 0 chroma ? three pixels (late) 1 1 1 not a valid setting auto_pdc_en; a utomatically programs the lta/cta values so that luma and chroma are aligned at the output for all modes of operation 0 use values in lta[1:0] and cta[ 2:0] for delaying luma/chroma 1 lta and cta values determined automatically swpc; allows the cr and cb samples to be swapped 0 no swapping 1 swap the cr and cb output samples 0x2b misc gain c ontrol pw_upd; peak white u pdate determines the rate of gain 0 update once per video line peak white must be enabled; see lagc[2:0] 1 update once per field reserved 1 0 0 0 0 set to default cke; color kill enable allows the color kill function to be swit ched on and off 0 color kill disabled for secam color kill, the threshold is set at 8%; see ckillthr[2:0] 1 color kill enabled reserved 1 set to default 0x2c agc m ode c ontrol cagc[1:0]; chroma auto - matic gain control selects the basic mode of operation for the agc in the chroma path 0 0 manual fixed gain use cmg[11:0] 0 1 use luma gain for chroma 1 0 automatic gain based on color burst 1 1 freeze chroma gain reserved 1 1 set to 1 lagc[2:0]; luma auto matic gain control selects the mode of operation for the gain control in the luma path 0 0 0 manual fixed gain use lmg[11:0] 0 0 1 peak white algorithm off blank level to sync tip 0 1 0 peak white algorit hm on blank level to sync tip 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 freeze gain reserved 1 set to 1 0x2d chroma gain control 1 , chroma gain1 (cg) cmg[11:8]/cg[11: 8]; in manual mode, the chroma gain control can be used to program a desired manual chroma gain; in auto mode, it can be used to read back the current gain value 0 1 0 0 cagc[1:0] settings decide in which mode cmg[11:0] operates reserved 1 1 set to 1 cagt[1:0]; chroma auto matic gain timing allows adjustment of the chroma agc tracking speed 0 0 slow (tc = 2 sec) has an effect o nly if cagc[1:0] is set to auto gain (10) 0 1 medium (tc = 1 sec) 1 0 reserved 1 1 adaptive
adv7180 data sheet rev. g | page 90 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x2e chroma gain control 2 , chroma gain2 (cg) cmg[7:0]/cg[7:0]; chroma manual gain lower eight bits; see cmg[11:8]/ cg[11:8] for description 0 0 0 0 0 0 0 0 cmg[11:0] = s ee the cmg section cmg[11:0] = s ee the cmg s e ction min value = 0d , max value = 4095d 0x2f luma gain control 1 , luma gain1 (lg) lmg[11:8]/lg[11:8]; in manual mode, luma gain control can be used to program a desired manual luma gain; in auto mode, it can be used to read back the actual gain value used x x x x lagc[1:0] settings decide in which mode lmg[11:0] operates reserved 1 1 set to 1 lagt[1:0]; luma auto matic gain timing allows adjustment of the luma agc tracking speed 0 0 slow (tc = 2 sec) only has an effe ct if lagc[1:0] is set to auto gain (001, 010, 011, or 100) 0 1 medium (tc = 1 sec) 1 0 fast (tc = 0.2 sec) 1 1 adaptive 0x30 luma gain control 2 , luma gain2 (lg) lmg[7:0]/lg[7:0]; luma manual gain lower eight bits; see lmg[11:8]/ lg[11:8] for de scription x x x x x x x x lmg[11:0] - s ee the lmg s ection lmg[11:0] = - s ee the lmg s ection min v alue = 1024d , max v alue = 4095d 0x31 vs/field control 1 reserved 0 1 0 set to default hvstim; selects where within a line of video the vs signal is as serted 0 start of line relative to hse hse = hsync end 1 start of line relative to hsb hsb = hsync begin newavmode; sets the eav/sav mode 0 eav/sav codes generated to suit analog devices encoders 1 manual vs/field po sition controlled by the 0x32, 0x33, and 0xe5 to 0xea registers reserved 0 0 0 set to default 0x32 vs/field control 2 reserved 0 0 0 0 0 1 set to default newavmode bit must be set high vsbhe 0 vs goes high in the middle of the line (even field) 1 vs changes state at the start of the line (even field) vsbho 0 vs goes high in the middle of the line (odd field) 1 vs changes state at the start of the line (odd field) 0x33 vs/field control 3 reserv ed 0 0 0 1 0 0 set to default vsehe 0 vs goes low in the middle of the line (even field) newavmode bit must be set high 1 vs changes state at the start of the line (even field) vseho 0 vs goes low in the middle of the l ine (odd field) 1 vs changes state at the start of the line odd field 0x34 hs position control 1 hse[10:8]; hs end allows positioning of the hs output within the video line 0 0 0 hs output ends hse[10:0] pixels after the falling edge of hsync using hsb and hse the user can program the position and length of the output hsync reserved 0 set to 0 hsb[10:8]; hs begin allows positioning of the hs output within the video line 0 0 0 hs output starts hsb[10:0] pixels aft er the falling edge of hsync reserved 0 set to 0 0x35 hs position control 2 hsb[7:0]; see address 0x34 , using hsb[10:0] and hse[10:0], users can program the position and length of the hs output signal 0 0 0 0 0 0 1 0 0x36 hs position co ntrol 3 hse[7:0]; see address 0x35 description 0 0 0 0 0 0 0 0
data sheet adv7180 rev. g | page 91 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x37 polarity pclk; sets polarity of llc 0 invert polarity 1 normal polarity as per the timing diagrams reserved 0 0 set to 0 pf; sets the field polarity 0 active high 1 active low reserved 0 set to 0 pvs; sets the vs polarity 0 active high 1 active low reserved 0 set to 0 phs; sets hs polarity 0 active low 1 active high 0x38 ntsc comb c ontrol ycmn[2:0]; luma comb mode, ntsc 0 0 0 adaptive three - line, three - tap luma 1 0 0 use low - pass notch 1 0 1 fixed luma comb (two - line) top lines of memory 1 1 0 fixed luma comb (three - line) all line s of memory 1 1 1 fixed luma comb (two - line) bottom lines of memory ccmn[2:0]; chroma comb mode, ntsc 0 0 0 three - line adaptive for ctapsn = 01 , fou r- line adaptive for ctapsn = 10, five - line adaptive for ctapsn = 11 1 0 0 disable chroma comb 1 0 1 fixed two - line for ctapsn = 01 , fixed three - line for ctapsn = 10 , fixed four - line for ctapsn = 11 top lines of memory 1 1 0 fixed three - line for ctapsn = 01 , fi xed four - line for ctapsn = 10 , fixed five - line for ctapsn = 11 all lines of memory 1 1 1 fixed two - line for ctapsn = 01 , fixed three - line for ctapsn = 10 , fixed four - line for ctapsn = 11 bottom lines of memory ctapsn[1:0]; chroma comb taps, ntsc 0 0 not used 0 1 adapts three lines to two lines 1 0 adapts five lines to three lines 1 1 adapts five lines to four lines 0x39 pal c omb ycmp[2:0]; luma com b mode, pal 0 0 0 adaptive five - line, three - tap luma comb c ontrol 1 0 0 use low - pass notch 1 0 1 fixed luma comb (three - line) top lines of memory 1 1 0 fixed luma comb (five - line) all lines of memory 1 1 1 fixed l uma comb (three - line) bottom lines of memory ccmp[2:0]; chroma comb mode, pal 0 0 0 three - line adaptive for ctapsn = 01 , four - line adaptive for ctapsn = 10 , five - line adaptive for ctapsn = 11 1 0 0 disable chroma comb 1 0 1 fix ed two - line for ctapsn = 01 top lines of memory fixed three - line for ctapsn = 10 fixed four - line for ctapsn = 11 1 1 0 fixed three - line for ctapsn = 01 all lines of memory fixed four - line for ctapsn = 10 fixed five - line for ctapsn = 11 1 1 1 fixed two - line for ctapsn = 01 bottom lines of memory fixed three - line for ctapsn = 10 fixed four - line for ctapsn = 11 ctapsp[1:0]; chroma comb taps, pal 0 0 not u sed 0 1 adapts five lines to three lines (two taps) 1 0 adapts five lines to three lines (three taps) 1 1 adapts five lines to four lines (four taps)
adv7180 data sheet rev. g | page 92 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x3a adc control mux pdn override; mux power-down override 0 no control over power-down for muxes and associ- ated channel circuit 1 allows power-down of mux0/mux1/ mux2 and associated channel circuit. when insel[3:0] is used, unused channels are automatically powered down. pwrdwn_mux_2; enables power-down of mux2 and associated channel clamp and buffer 0 mux2 and associated channel in normal operation 1 power down mux2 and associated channel operation mux pdn override = 1 pwrdwn_mux_1; enables power-down of mux1 and associated channel clamp and buffer 0 mux1 and associated channel in normal operation 1 power down mux1 and associated channel operation mux pdn override = 1 pwrdwn_mux_0; enables power-down of mux0 and associated channel clamp and buffer 0 mux0 and associated channel in normal operation 1 power down mux0 and associated channel operation mux pdn override = 1 reserved 0 0 0 1 set as default 0x3d manual window control reserved 0 0 1 0 set to default ckillthr[2:0] 0 0 0 ntsc, pal color kill at <0.5%, secam no color kill cke = 1 enables the color kill function and must be enabled for ckillthr[2:0] to take effect 0 0 1 ntsc, pal color kill at <1.5%, secam color kill at <5% 0 1 0 ntsc, pal color kill at <2.5%, secam color kill at <7% 0 1 1 ntsc, pal color kill at <4%, secam color kill at <8% 1 0 0 ntsc, pal color kill at <8.5%, secam color kill at <9.5% 1 0 1 ntsc, pal color kill at <16%, secam color kill at <15% 1 1 0 ntsc, pal color kill at <32%, secam color kill at <32% 1 1 1 reserved reserved 1 set to default 0x41 resample control reserved 0 0 0 0 0 1 set to default sfl_inv; controls the behavior of the pal switch bit 0 sfl-compatible with the adv717x and adv73xx video encoders 1 sfl-compatible with the adv7194 video encoder reserved 0 set to default 0x48 gemstar control 1 gdecel[15:8]; see the comments column 0 0 0 0 0 0 0 0 gdecel[15:0]: 16 individual enable bits that select the lines of video (even field line 10 to line 25) that the decoder checks for gemstar-compatible data lsb = line 10, msb = line 25, default = do not check for gemstar- compatible data on any lines [10 to 25] in even fields 0x49 gemstar control 2 gdecel[7:0] 0 0 0 0 0 0 0 0
data sheet adv7180 rev. g | page 93 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x4a gemstar control 3 gdecol[15:8]; see the comments column 0 0 0 0 0 0 0 0 gdecol[15:0]: 16 individual enable bits that select the lines of video (odd field line 10 to line 25) that the decoder checks for gemstar - compatible data lsb = line 10 , msb = line 25 , default = do not check for gemstar - compatible data on any lines [10 to 25] in odd fields 0x4b gemstar control 4 gdecol[7:0] 0 0 0 0 0 0 0 0 0x4c gemstar control 5 gdecad; controls the manner decoded gemstar data is inserted into the horizontal blanking period 0 split data into half - byte to avoid 00/ff code 1 output in straight 8 - bit format gde_sel_old_adf 0 enab les a new ancillary data system reserved x x x x x x undefined 0x4d cti dnr control 1 cti_en; cti enable 0 disable cti 1 enable cti cti_ab_en; enables the mixing of the transient improved chroma with the original signal 0 disable cti alpha blender 1 enable cti alpha blender cti_ab[1:0]; controls the behavior of the alpha - blend circuitry 0 0 sharpest mixing 0 1 sharp mixing 1 0 smooth mixing 1 1 smoothest mixing reserved 0 set to default dnr_en; enable or bypass the dnr block 0 bypass the dnr block 1 enable the dnr block reserved 1 1 set to default 0x4e cti dnr control 2 cti_c_th[7:0]; specifies how big the amplitude step must be to be steep - ened by the cti block 0 0 0 0 1 0 0 0 set to 0x04 for av input; set to 0x0a for tuner input 0x50 cti dnr control 4 dnr_th[7:0]; specifies the maximum edge that is interpreted as noise and is therefore blanked 0 0 0 0 1 0 0 0 0x51 lock c ount cil[2:0]; count into lock determines the number of lines the system must remain in lock before showing a locked status 0 0 0 one line of video 0 0 1 two lines of video 0 1 0 five lines of video 0 1 1 10 lines of video 1 0 0 100 lines of video 1 0 1 500 lines of video 1 1 0 1000 lines of video 1 1 1 100,000 lines of video col[2:0]; count out of lock determines the number of lines the system must remai n out - of - lock before showing a lost - locked status 0 0 0 1 line of video 0 0 1 2 lines of video 0 1 0 5 lines of video 0 1 1 10 lines of video 1 0 0 100 lines of video 1 0 1 500 lines of video 1 1 0 1000 lines of video 1 1 1 100,000 lines of video s rls; select raw lock signal; s elects the determination of the lock status 0 over field with vertical info 1 line - to - line evaluation fscle; f sc lock enable 0 lock status set only by horizontal lock 1 lock status set by horizontal lock and subcarrier lock 0x58 vs/field p in c ontrol vs/field; vsync or field output; 40- lead and 32- lead lfcsp only 0 field pin 37 on 40- lead lfcsp , pin 3 1 on 32- lead lfcsp 1 vsync reserved 0 set to default adc sampling control 0 adc sampling control 1 y/c mode only mandatory write reserved 0 0 0 0 0 set to default
adv7180 data sheet rev. g | page 94 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0x59 general - purpose o utputs gpo[3:0]; lqfp only 0 outputs 0 to gpo0 gpo_ enable must be set to 1 for these bits to take effect 1 outputs 1 to gpo0 0 outputs 0 to gpo1 1 outputs 1 to gpo1 0 outputs 0 to gpo2 1 outputs 1 to gpo2 0 outputs 0 to gpo3 1 outputs 1 to gpo3 gpo_ enable 0 gpo[3:0] three - stated 1 gpo[3:0] enabled reserved 0 0 0 0x8f free - run line length 1 reserved 0 0 0 0 set to default llc_pad_sel[2:0]; enables manual selection of the clock for the llc pin 0 0 0 llc (nominal 27 mhz) selected out on llc pin 1 0 1 llc (nominal 13.5 mhz) selected out on llc pin for 16 - bit 4:2:2 out, of_sel[3:0] = 0010 reserved 0 set to default 0x9 9 ccap1 (r ead o nly) ccap1[7:0] ; closed caption data register x x x x x x x x ccap1[7] contains parity bit for byte 0 0x9a ccap2 (r ead o nly) ccap2[7:0] ; closed caption data register x x x x x x x x ccap2[7] contains parity bit for byte 0 0x9b letterbox 1 (r ead o nly) lb_lct[7:0]; l etterbox data register x x x x x x x x reports the number of black lines detected at the top of active video this feature examines the active video at the start and end of each field; it enables format detection even if th e video is not accompanied by a cgms or wss sequence 0x9c letterbox 2 (r ead o nly) lb_lcm[7:0]; l etterbox data register x x x x x x x x reports the number of black lines detected in the bottom half of active video if subtitles are detected 0x9d lett erbox 3 (r ead o nly) lb_lcb[7:0]; l etterbox data register x x x x x x x x reports the number of black lines detected at the bottom of active video 0xb2 crc e nable (w rite o nly) reserved 0 0 set as default crc_enable; enable crc checksum decoded from fms packet to validate cgmsd 0 turn off crc check 1 cgmsd goes high with valid checksum reserved 0 0 0 1 1 set as default 0xc3 adc switch 1 mux0[2:0]; manual muxing control for mux0; this setting controls which input is routed to the adc for processing lqfp lfcsp man_mux_en = 1 0 0 0 no connect no connect 0 0 1 a in 1 a in 1 0 1 0 a in 2 no connect 0 1 1 a in 3 no connect 1 0 0 a in 4 a in 2 1 0 1 a in 5 a in 3 1 1 0 a in 6 no connect 1 1 1 no connect no connect reserved 0 mux1[2:0]; manual muxing control for mux1; this setting controls which input is routed to the adc for processing lqfp lfcsp man_mux_en = 1 0 0 0 no connect no connect 0 0 1 no connect no connect 0 1 0 no connect no connect 0 1 1 a in 3 no connect 1 0 0 a in 4 a in 2 1 0 1 a in 5 a in 3 1 1 0 a in 6 no connect 1 1 1 no connect no connect reserved 0
data sheet adv7180 rev. g | page 95 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0xc4 adc switch 2 mux2[2:0]; manual muxing control for mux2; this setting controls which input is routed to the adc for processing lqfp lfcsp man_mux_en = 1 0 0 0 no connect no connect 0 0 1 no connec t no connect 0 1 0 a in 2 no connect 0 1 1 no connect no connect 1 0 0 no connect no connect 1 0 1 a in 5 a in 3 1 1 0 a in 6 no connect 1 1 1 no connect no connect reserved 0 0 0 0 man_mux_e n; enable manual setting of the input signal muxing 0 disable this bit must be set to 1 for manual muxing 1 enable 0xdc letterbox control 1 lb_th[4:0]; sets the threshold value that determines if a line is black 0 1 1 0 0 defau lt threshold for the detection of black lines 01101 to 10000 increase threshold , 00000 to 01011 decrease threshold reserved 1 0 1 set as default 0xdd letterbox control 2 lb_el[3:0]; programs the end line of the activity window for lb detection (end of field) 1 1 0 0 lb detection ends with the last line of active video on a field, 1100b: 262/525 lb_sl[3:0]; programs the start line of the activity window for lb detection (start of field) 0 1 0 0 letterbox detection aligned with the start of active video, 0100b: 23/286 ntsc 0xde st noise readback 1 (r ead o nly) st_noise[10:8] x x x st_noise_vld x when = 1, st_noise[10:0] is valid 0xdf st noise readback 2 (r ead o nly) st_noise[7:0] x x x x x x x x 0xe1 sd offse t cb sd_off_cb[7:0]; adjusts the hue by selecting the offset for the cb channel 0 0 0 0 0 0 0 0 ?312 mv offset applied to the cb channel 1 0 0 0 0 0 0 0 0 mv offset applied to the cb channel 1 1 1 1 1 1 1 1 + 312 mv offset applied to the cb channel 0xe2 sd offset cr sd_off_cr[7:0]; adjusts the hue by selecting the offset for the cr cha nnel 0 0 0 0 0 0 0 0 ?312 mv offset applied to the c r channel 1 0 0 0 0 0 0 0 0 mv offset applied to the cr channel 1 1 1 1 1 1 1 1 + 312 mv offset applied to the cr channel 0xe3 sd saturation cb sd_sat_cb[7:0]; adjusts the saturation by affect ing gain on the cb channel 0 0 0 0 0 0 0 0 gain on cb channel = ?42 db 1 0 0 0 0 0 0 0 gain on cb channel = 0 db 1 1 1 1 1 1 1 1 gain on cb channel = +6 db 0xe4 sd saturation cr sd_sat_cr[7:0]; adjusts the saturation by affecting gain on the cr channel 0 0 0 0 0 0 0 0 gain on cr channel = ?42 db 1 0 0 0 0 0 0 0 gain on cb channel = 0 db 1 1 1 1 1 1 1 1 gain on cb channel = +6 db 0xe5 ntsc v bit b egin nvbeg[4:0]; number of lines after l count rollover to set v high 0 0 1 0 1 nt sc default (itu - r bt.656) nvbegsign 0 set to low when manual programming 1 not suitable for user programming nvbegdele; delay v bit going high by one line relative to nvbeg (even field) 0 no delay 1 addit ional delay by one line nvbegdelo; delay v bit going high by one line relative to nvbeg (odd field) 0 no delay 1 additional delay by one line
adv7180 data sheet rev. g | page 96 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0xe6 ntsc v b it e nd nvend[4:0]; number of lines after l count rollover to set v lo w 0 0 1 0 0 ntsc default (itu - r bt.656) nvendsign 0 set to low when manual programming 1 not suitable for user programming nvenddele; delay v bit going low by one line relative to nvend (even field) 0 no delay 1 additional delay by one line nvenddelo; delay v bit going low by one line relative to nvend (odd field) 0 no delay 1 additional delay by one line 0xe7 ntsc f bit t oggle nftog[4:0]; number of lines after l count ro llover to toggle f signal 0 0 0 1 1 ntsc default nftogsign 0 set to low when manual programming 1 not suitable for user programming nftogdele; delay f transition by one line relative to nftog (even field) 0 no del ay 1 additional delay by one line nftogdelo; delay f transition by one line relative to nftog (odd field) 0 no delay 1 additional delay by one line 0xe8 pal v b it b egin pvbeg[4:0]; number of lines after l count r ollover to set v high 0 0 1 0 1 pal default ( itu - r bt.656) pvbegsign 0 set to low when manual programming 1 not suitable for user programming pvbegdele; delay v bit going high by one line relative to pvbeg (even field) 0 no delay 1 additional delay by one line pvbegdelo; delay v bit going high by one line relative to pvbeg (odd field) 0 no delay 1 additional delay by one line 0xe9 pal v b it e nd pvend[4:0]; number of line s after l count rollover to set v low. 1 0 1 0 0 pal default ( itu - r bt.656) pvendsign 0 set to low when manual programming 1 not suitable for user programming pvenddele; delay v bit going low by one line relative to pvend (even field) 0 no delay 1 additional delay by one line pvenddelo; delay v bit going low by one line relative to pvend (odd field) 0 no delay 1 additional delay by one line 0xea pal f b it t oggle pftog[4:0] ; number of lines after l count rollover to toggle f signal 0 0 0 1 1 pal default ( itu - r bt.656) pftogsign 0 set to low when manual programming 1 not suitable for user programming pftogdele; delay f transition by one line r elative to pftog (even field) 0 no delay 1 additional delay by one line pftogdelo; delay f transition by one line relative to pftog (odd field) 0 no delay 1 additional delay by one line
data sheet adv7180 rev. g | page 97 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0xeb vblank control 1 pvbielcm[1:0]; pal vbi even field line control 0 0 vbi ends one line earlier (line 335) controls position of first active (comb filtered) line after vbi on even field in pal 0 1 itu - r bt.470 compliant (line 336) 1 0 vbi end s one line later (line 337) 1 1 vbi ends two lines later (line 338) pvbiolcm[1:0]; pal vbi odd field line control 0 0 vbi ends one line earlier (line 22) controls position of first active (comb filtered) line after vbi on odd field in pal 0 1 itu - r bt.470 compliant (line 23) 1 0 vbi ends one line later (line 24) 1 1 vbi ends two lines later (line 25) nvbielcm[1:0]; ntsc vbi even field line control 0 0 vbi ends one line earlier (line 282) con trols position of first active (comb filtered) line after vbi on even field in ntsc 0 1 itu - r bt.470 compliant (line 283) 1 0 vbi ends one line later (line 284) 1 1 vbi ends two lines later (line 285) nvbiolcm[1:0]; ntsc vbi odd field line control 0 0 vbi ends one line earlier (line 20) controls position of first active (comb filtered) line after vbi on odd field in ntsc 0 1 itu - r bt.470 compliant (line 21) 1 0 vbi ends one line later (line 2 2) 1 1 vbi ends two lines later (line 23) 0xec vblank control 2 pvbieccm[1:0]; pal vbi even field color control 0 0 color output beginning line 335 controls the position of first line that outputs color after vbi on even field in pa l 0 1 itu - r bt.470 compliant color output beginning line 336 1 0 color output beginning line 337 1 1 color output beginning line 338 pvbioccm[1:0]; pal vbi odd field color control 0 0 color output beginning line 2 2 controls the position of first line that outputs color after vbi on odd field in pal 0 1 itu - r bt.470 - compliant color output beginning line 23 1 0 color output beginning line 24 1 1 color output beginning line 25 n vbieccm[1:0]; ntsc vbi even field color control 0 0 color output beginning line 282 controls the position of first line that outputs color after vbi on even field in ntsc 0 1 itu - r bt.470 - compliant color output beginning line 283 1 0 vbi ends one line later (line 284) 1 1 color output beginning line 285 nvbioccm[1:0]; ntsc vbi odd field color control 0 0 color output beginning line 20 controls the position of first line that outputs color after vbi on odd f ield in ntsc 0 1 itu - r bt.470 compliant color output beginning line 21 1 0 color output beginning line 22 1 1 color output beginning line 23 0xf3 afe_control 1 aa_filt_en[2:0]; a ntialiasing filter enable 0 antiali asing filter 1 disabled aa_filt_man_ovr must be enabled to change settings defined by insel[3:0] 1 antialiasing filter 1 enabled 0 antialiasing filter 2 disabled 1 antialiasing filter 2 enabled 0 antialiasing filter 3 disabled 1 antialiasing filter 3 enabled aa_filt_man_ovr; antialiasing filter override 0 override disabled 1 override enabled reserved 0 0 0 0
adv7180 data sheet rev. g | page 98 of 120 subaddress register bit description bits (shading indicates default state) comments notes 7 6 5 4 3 2 1 0 0xf4 drive s trength dr_str_s[1:0]; s elects the drive str ength for the sync output signals 0 0 low drive strength (1) 0 1 medium low drive strength (2) 1 0 medium high drive strength (3) 1 1 high drive strength (4) dr_str_c[1:0]; s elects the drive strength for the clock output signal 0 0 low drive strength (1) 0 1 medium low drive strength (2) 1 0 medium high drive strength (3) 1 1 high drive strength (4) dr_str[1:0]; selects the drive strength for the data output sign als; can be increased or decreased for emc or crosstalk reasons 0 0 low drive strength (1) 0 1 medium low drive strength (2) 1 0 medium high drive strength (3) 1 1 high drive strength (4) reserved x x 0xf8 if comp c ontrol iffiltsel[2:0]; i f filter selection for pal and ntsc 0 0 0 bypass mode 0 db 2 mhz 5 mhz ntsc filters 0 0 1 ? 3 db ? 2 db 0 1 0 ? 6 db +3.5 db 0 1 1 ? 10 db +5 db 1 0 0 reserved 3 mhz 6 mhz pal filters 1 0 1 ? 2 db +2 db 1 1 0 ? 5 db +3 db 1 1 1 ? 7 db +5 db reserved 0 0 0 0 0 0xf9 vs mode c ontrol extend_vs_max_freq 0 limits maximum vsync frequency to 66.25 hz (475 lines/frame) 1 limits maximum vsync frequency to 70.09 hz (449 lines/frame) extend_vs_min_freq 0 limits minimum vsync frequency to 42.75 hz (731 lines/frame) 1 limits minimum vsync frequency to 39.51 hz (791 lines/frame) vs_coast _mode[1:0] 0 0 autocoast mode this value sets up the output coast frequency 0 1 50 hz coast mode 1 0 60 hz coast mode 1 1 reserved reserved 0 0 0 0 0xfb peaking c ontrol peaking_gain[7:0] 0 1 0 0 0 0 0 0 inc reases/decreases the gain for high frequency portions of the video signal 0xfc coring t hreshold dnr_th2[7:0] 0 0 0 0 0 1 0 0 specifies the maximum edge that is interpreted as noise and therefore blanked 1 shading indicates default values. 2 x indicates a bit that keeps the last written value.
data sheet adv7180 rev. g | page 99 of 120 table 108 . register m ap descriptions (interrupt operation) 1, 2 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x40 interrupt configuration 1 intrq_op_sel[1:0]; interrupt drive level select 0 0 open drain 0 1 drive low when active 1 0 drive high when active 1 1 reserved mpu_stim_intrq; manual interrupt set mode 0 manual interrupt mode disabled 1 manual interrupt mode enabled reserved x not used mv_intrq_sel[1:0]; macrovision interrupt select 0 0 reserved 0 1 pseudo sync only 1 0 color stripe only 1 1 pseudo sync or color stripe intrq_dur_sel[1:0]; interrupt duration select 0 0 th ree xtal periods 0 1 15 xtal periods 1 0 63 xtal periods 1 1 active until cleared 0x42 interrupt status 1 (read o nly) sd_lock_q 0 no change these bits can be cleared or masked in register 0x43 and register 0x44, res - pec tively 1 sd input has caused the decoder to go from an unlocked state to a locked state sd_unlock_q 0 no change 1 sd input has caused the decoder to go from a locked state to an unlocked state reserved x x x sd_fr_chng_q 0 no change 1 denotes a change in the free - run status mv_ps_cs_q 0 no change 1 pseudo sync/color striping detected; see reg ister 0x40 mv_intrq_sel[1:0] for selection reserved x 0x43 interrup t clear 1 (write o nly) sd_lock_clr 0 do not clear 1 clears sd_lock_q bit sd_unlock_clr 0 do not clear 1 clears sd_unlock_q bit reserved 0 0 0 not used sd_fr_chng_clr 0 do not cl ear 1 clears sd_fr_chng_q bit mv_ps_cs_clr 0 do not clear 1 clears mv_ps_cs_q bit reserved x not used 0x44 interrupt mask 1 (r ead/ w rite) sd_lock_msk 0 masks sd_lock_q bit 1 unmasks sd_lock_q bit sd_unlock_msk 0 masks sd_unlock_q bit 1 unmasks sd_unlock_q bit reserved 0 0 0 not used sd_fr_chng_msk 0 masks sd_fr_chng_q bit 1 unmasks sd _fr_chng_q bit mv_ps_cs_msk 0 masks mv_ps_cs_q bit 1 unmasks mv_ps_cs_q bit reserved x not used
adv7180 data sheet rev. g | page 100 of 120 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x45 raw status 2 (r ead o nly) ccapd 0 no ccapd data detected vbi system 2 these bits are status bits only; they cannot be cleared or masked; register 0x46 is used for this purpose 1 ccapd data detected vbi system 2 reserved x x x even_field 0 current sd field is odd numbered 1 current sd field is even nu mbered reserved x x mpu_stim_intrq 0 mpu_stim_intrq = 0 1 mpu_stim_intrq = 1 0x46 interrupt status 2 (r ead o nly) ccapd_q 0 closed captioning not detected in the input video signal vbi system 2 these bits can be cl eared or masked by register 0x47 and register 0x48, res - pectively; n ote that the interrupt in register 0x46 for the ccap, gemstar, cgms, and wss data uses the mode 1 data slicer 1 closed captioning data detected in the video input signal vbi system 2 gemd_q 0 gemstar data not detected in the input video signal vbi system 2 1 gemstar data detected in the input video signal vbi system 2 reserved x x sd_field_chngd_q 0 sd signal has not changed fiel d from odd to even or vice versa 1 sd signal has changed field from odd to even or vice versa reserved x not used reserved x not used mpu_stim_intrq_q 0 manual interrupt not set 1 manual interrupt set 0x47 interrupt clear 2 (w rite o nly) ccapd_clr 0 do not clear vbi system 2 note that interrupt in register 0x46 for the ccap, gemstar, cgms, and wss data us es the mode 1 data slicer 1 clears ccapd_q bit vbi system 2 gemd_clr 0 do not clear 1 clears gemd_q bit reserved 0 0 sd_field_chngd_clr 0 do not clear 1 clears sd_field_chngd_q bit reserved x x not used mpu_stim_intrq_clr 0 do not clear 1 clears mpu_stim_intrq_q bit 0x48 interrupt mask 2 (r ead/ w rite) ccapd_msk 0 masks ccapd_q bit vbi system 2 note that interrupt in register 0x46 for the ccap, gemstar, cgms, and wss data uses the mode 1 data slicer 1 unmasks ccapd_q bit vbi system 2 gemd_msk 0 masks gemd_q bit vbi system 2 1 unmasks gemd_q bit vbi system 2 reserved 0 0 not used sd_field_chngd_msk 0 masks sd_field_chngd_q bit 1 unmasks sd_field_chngd_q bit reserved 0 0 not used mpu_stim_intrq_msk 0 masks mpu_stim_intrq_q bit 1 unmasks mpu_stim_intrq_q bit 0x49 raw status 3 (r ead o nly) sd_op_50hz; sd 60 hz/50 hz frame rate at output 0 sd 60 hz signal output these bits are status bits only; they cannot be cleared or masked; register 0x4a is used for this purpose 1 sd 50 hz signal output sd_v_lock 0 sd vertical sync lock not esta blished 1 sd vertical sync lock established sd_h_lock 0 sd horizontal sync lock not established 1 sd horizontal sync lock established reserved x not used scm_lock 0 secam lock not established 1 secam lock established reserved x x x not used
data sheet adv7180 rev. g | page 101 of 120 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x4a interrupt status 3 (r ead o nly) sd_op_chng_q; sd 60 hz/50 hz frame rate at output 0 no change in sd signal standard detected at the output these bits can be cleared and masked b y register 0x4b and register 0x4c, respectively 1 a change in sd signal standard is detected at the output sd_v_lock_chng_q 0 no change in sd vsync lock status 1 sd vsync lock status has changed sd_h_lock_chng_q 0 no change in hsync lock status 1 sd hsync lock status has changed sd_ad_chng_q; sd autodetect changed 0 no change in ad_result[2:0] bits in status 1 r egister 1 ad_result[2:0] bits in status 1 register ha ve changed scm_lock_chng_q; secam lock 0 no change in secam lock status 1 secam lock status has changed pal_sw_lk_chng_q 0 no change in pal swinging burst lock status 1 pal swinging burst lock status has changed res erved x x not used 0x4b interrupt clear 3 (w rite o nly) sd_op_chng_clr 0 do not clear 1 clears sd_op_chng_q bit sd_v_lock_chng_clr 0 do not clear 1 clears sd_v_lock_chng_q bit sd_h_lock_chng_clr 0 do not clear 1 clears sd_h_lock_chng_q bit sd_ad_chng_clr 0 do not clear 1 clears sd_ad_chng_q bit scm_lock_chng_clr 0 do not clear 1 clears scm_lock_chng_q bit pal_sw_lk_chng_clr 0 do not clear 1 clears pal_sw_lk_chng_q bit reserved x x not used 0x4c interrupt mask 3 (read/w rite) sd_op_chng_msk 0 masks sd_op_chng_q bit 1 unmasks sd_op_chng_q bit sd_v_lock_ch ng_msk 0 masks sd_v_lock_chng_q bit 1 unmasks sd_v_lock_chng_q bit sd_h_lock_chng_msk 0 masks sd_h_lock_chng_q bit 1 unmasks sd_h_lock_chng_q bit sd_ad_chng_msk 0 m asks sd_ad_chng_q bit 1 unmasks sd_ad_chng_q bit scm_lock_chng_msk 0 masks scm_lock_chng_q bit 1 unmasks scm_lock_chng_q bit pal_sw_lk_chng_msk 0 masks pal_sw_lk_chng_q bit 1 unmasks pal_sw_lk_chng_q bit reserved x x not used 0x4e interrupt status 4 (r ead o nly) vdp_ccapd_q 0 closed captioning not detected these bits can be cleared and masked by register 0x4f and register 0x50, respectively; not e that an interrupt in register 0x4e for the ccap, gemstar, cgms, wss, vps, pdc, utc, and vitc data uses the vdp data slicer 1 closed captioning detected reserved x vdp_cgms_wss_chngd_q; see 0x9c bit 4 of user sub map to dete rmine whether interrupt is issued for a change in detected data or for when data is detected regardless of content 0 cgms/wss data is not changed/ not available 1 cgms/wss data is changed/available reserved x vdp_gs_vp s_pdc_utc_chng_q; see 0x9c bit 5 o f user sub map to deter - mine whether interrupt is issued for a change in detected data or for when data is detected regardless of content 0 gemstar/pdc/vps/utc data is not changed/ not available 1 gemstar /pdc/vps/utc data is changed/available reserved x vdp_vitc_q 0 vitc data is not available in the vdp 1 vitc data is available in the vdp reserved x
adv7180 data sheet rev. g | page 102 of 120 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x4f interrup t clear 4 (w rite o nly) vdp_ccapd_clr 0 do not clear note that an interrupt in register 0x4e for the ccap, gemstar, cgms, wss, vps, pdc, utc, and vitc data uses the vdp data slicer 1 clears vdp_ccapd_q reserved 0 vdp_cgms_wss_chngd_clr 0 do not clear 1 clears vdp_cgms_wss_chngd_q reserved 0 vdp_gs_vps_pdc_utc_chng_clr 0 do not clear 1 clears vdp_gs_vps_pdc_utc_chng_q reserved 0 vdp_vitc_clr 0 do not clear 1 clears vdp_vitc_q reserved 0 0x50 interrupt mask 4 vdp_ccapd_msk 0 masks vdp_ccapd_q note that an interrupt in register 0x4e for the ccap, gemstar, cgms, wss, vps, pdc, utc, and vitc data uses the vdp data slicer 1 unmasks vdp_ccapd_q reserved 0 vdp_cgms_wss_chngd_msk 0 masks vdp_cgms_wss_chngd_q 1 unmasks vdp_cgms_wss_chngd_q reserved 0 vdp_gs_vps_pdc_utc_chng_msk 0 masks vdp_gs_vp s_pdc_utc_chng_q 1 unmasks vdp_gs_vps_pdc_utc_ chng_q reserved 0 vdp_vitc_msk 0 masks vdp_vitc_q 1 unmasks vdp_vitc_q reserved 0 0x60 vdp_config_1 vdp_ttxt_type_man[1:0] 0 0 pal: tele text - itu - bt.653 - 625/50 -a, ntsc: r eserved 0 1 pal: teletext - itu - bt.653 - 625/50 - b (wst) , ntsc: teletext - itu - bt.653 - 525/60 -b 1 0 pal: teletext - itu - bt.653 - 625/50 -c, ntsc: teletext - itu - bt.653 - 525/60 -c, or eia516 (nabts) 1 1 pal: teletext - itu - bt.653 - 625/50 -d, ntsc: teletext - itu - bt.653 - 525/60 -d vdp_ttxt_type_man_enable 0 user programming of teletext type disabled 1 user programming of teletext type enabled wst_pkt_decode_disable 0 enable hamming decoding of wst packets 1 disable hamming decoding of wst packets reserved 1 0 0 0 0x61 vdp_config_2 reserved x x 0 0 auto_detect_gs_type 0 disable autodetection of gemstar type 1 enable autodetection of gemstar type reserved 0 0 0 0x62 vdp_adf_config_1 adf_did[4:0] 1 0 1 0 1 user - specified did sent in the ancillary data stream with vdp decoded data adf_mode[1:0] 0 0 nibble mode 0 1 byte mode, no code restricti ons 1 0 byte mode with 0x00 and 0xff prevented 1 1 reserved adf_enable 0 disable insertion of vbi decoded data into ancillary 656 stream 1 enable insertion of vbi decoded data into ancillary 656 stream 0x63 vdp_adf_config_2 adf_sdid[5:0] 1 0 1 0 1 0 user - specified sdid sent in the ancillary data stream with vdp decoded data reserved x duplicate_adf 0 ancillary data packet is spread across the y and c data streams 1 anci llary data packet is duplicated on the y and c data streams
data sheet adv7180 rev. g | page 103 of 120 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x64 vdp_line_00e vbi_data_p318[3:0] 0 0 0 0 sets vbi standard to be decoded from line 318 (pal), ntsc n/a reserved 0 0 0 man_line_pgm 0 decode default standards on th e lines indicated in table 69 1 manually program the vbi standard to be decoded on each line; see table 70 if set to 1, all vbi_data_ px_ny bits can b e set as desired 0x65 vdp_line_00f vbi_data_p319_n286[3:0] 0 0 0 0 sets vbi standard to be decoded from line 319 (pal), line 286 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p6_n23[3:0] 0 0 0 0 sets vbi stand ard to be decoded from line 6 (pal), line 23 (ntsc) 0x66 vdp_line_010 vbi_data_p320_n287[3:0] 0 0 0 0 sets vbi standard to be decoded from line 320 (pal), line 287 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p7 _n24[3:0] 0 0 0 0 sets vbi standard to be decoded from line 7 (pal), line 24 (ntsc) 0x67 vdp_line_011 vbi_data_p321_n288[3:0] 0 0 0 0 sets vbi standard to be decoded from line 321 (pal), line 288 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p8_n25[3:0] 0 0 0 0 sets vbi standard to be decoded from line 8 (pal), line 25 (ntsc) 0x68 vdp_line_012 vbi_data_p322[3:0] 0 0 0 0 sets vbi standard to be decoded from line 322 (pal), ntsc n/a man_line_pgm must be set to 1 for these bits to be effective vbi_data_p9[3:0] 0 0 0 0 sets vbi standard to be decoded from line 9 (pal), ntsc n/a 0x69 vdp_line_013 vbi_data_p323[3:0] 0 0 0 0 sets vbi standard to be decoded from line 323 (pal), ntsc n/a man _line_pgm must be set to 1 for these bits to be effective vbi_data_p10[3:0] 0 0 0 0 sets vbi standard to be decoded from line 10 (pal), ntsc n/a 0x6a vdp_line_014 vbi_data_p324_n272[3:0] 0 0 0 0 sets vbi standard to be decoded from line 32 4 (pal), line 272 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p11[3:0] 0 0 0 0 sets vbi standard to be decoded from line 11 (pal); ntsc n/a 0x6b vdp_line_015 vbi_data_p325_n273[3:0] 0 0 0 0 sets vbi standard to be decoded from line 325 (pal), line 273 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p12_n10[3:0] 0 0 0 0 sets vbi standard to be decoded from line 12 (pal), line 10 (ntsc) 0x6c vdp_line_016 vbi_data_p326_n 274[3:0] 0 0 0 0 sets vbi standard to be decoded from line 326 (pal), line 274 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p13_n11[3:0] 0 0 0 0 sets vbi standard to be decoded from line 13 (pal), line 11 (nts c) 0x6d vdp_line_017 vbi_data_p327_n275[3:0] 0 0 0 0 sets vbi standard to be decoded from line 327 (pal), line 275 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p14_n12[3:0] 0 0 0 0 sets vbi standard to be dec oded from line 14 (pal), line 12 (ntsc) 0x6e vdp_line_018 vbi_data_p328_n276[3:0] 0 0 0 0 sets vbi standard to be decoded from line 328 (pal), line 276 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p15_n13[3:0] 0 0 0 0 sets vbi standard to be decoded from line 15 (pal), line 13 (ntsc) 0x6f vdp_line_019 vbi_data_p329_n277[3:0] 0 0 0 0 sets vbi standard to be decoded from line 329 (pal), line 277 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p16_n14[3:0] 0 0 0 0 sets vbi standard to be decoded from line 16 (pal), line 14 (ntsc) 0x70 vdp_line_01a vbi_data_p330_n278[3:0] 0 0 0 0 sets vbi standard to be decoded from line 330 (pal), line 278 (ntsc) man_line_pgm m ust be set to 1 for these bits to be effective vbi_data_p17_n15[3:0] 0 0 0 0 sets vbi standard to be decoded from line 17 (pal), line 15 (ntsc) 0x71 vdp_line_01b vbi_data_p331_n279[3:0] 0 0 0 0 sets vbi standard to be decoded from line 331 (pal), line 279 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p18_n16[3:0] 0 0 0 0 sets vbi standard to be decoded from line 18 (pal), line 16 (ntsc) 0x72 vdp_line_01c vbi_data_p332_n280[3:0] 0 0 0 0 sets vbi standard to be decoded from line 332 (pal), line 280 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p19_n17[3:0] 0 0 0 0 sets vbi standard to be decoded from line 19 (pal), line 17 (ntsc) 0x73 vdp_line_01d vbi_da ta_p333_n281[3:0] 0 0 0 0 sets vbi standard to be decoded from line 333 (pal), line 281 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p20_n18[3:0] 0 0 0 0 sets vbi standard to be decoded from line 20 (pal), lin e 18 (ntsc)
adv7180 data sheet rev. g | page 104 of 120 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x74 vdp_line_01e vbi_data_p334_n282[3:0] 0 0 0 0 sets vbi standard to be decoded from line 334 (pal), line 282 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p21_n19[3:0] 0 0 0 0 sets vbi standard to be decoded from line 21 (pal), line 19 (ntsc) 0x75 vdp_line_01f vbi_data_p335_n283[3:0] 0 0 0 0 sets vbi standard to be decoded from line 335 (pal), line 283 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p22_n20[ 3:0] 0 0 0 0 sets vbi standard to be decoded from line 22 (pal), line 20 (ntsc) 0x76 vdp_line_020 vbi_data_p336_n284[3:0] 0 0 0 0 sets vbi standard to be decoded from line 336 (pal), line 284 (ntsc) man_line_pgm must be set to 1 for these bits to be effective vbi_data_p23_n21[3:0] 0 0 0 0 sets vbi standard to be decoded from line 23 (pal), line 21 (ntsc) 0x77 vdp_line_021 vbi_data_p337_n285[3:0] 0 0 0 0 sets vbi standard to be decoded from line 337 (pal), line 285 (ntsc) man_lin e_pgm must be set to 1 for these bits to be effective vbi_data_p24_n22[3:0] 0 0 0 0 sets vbi standard to be decoded from line 24 (pal), line 22 (ntsc) 0x78 vdp_status (r ead o nly) cc_avl 0 closed captioning not detected cc_clear resets th e cc_avl bit 1 closed captioning detected cc_even_field 0 closed captioning decoded from odd field 1 closed captioning decoded from even field cgms_wss_avl 0 cgms/wss not detected cgms_wss_clear resets the cg ms_wss_avl bit 1 cgms/wss detected reserved 0 gs_pdc_vps_utc_avl 0 gs/pdc/vps/utc not detected gs_pdc_vps_utc_clear resets the gs_pdc_vps_utc_avl bit 1 gs/pdc/vps/utc detected gs_data_type 0 gemstar_ 1 detected 1 gemstar_2 detected vitc_avl 0 vitc not detected vitc_clear resets the vitc_avl bit 1 vitc detected ttxt_avl 0 teletext not detected 1 teletext detected vdp_status_ clear (w rite o nly) cc_clear 0 does not reinitialize the ccap readback registers this is a self - clearing bit 1 reinitializes the ccap readback registers reserved 0 cgms_wss_clear 0 does not reinitialize the cgms/wss readback registers this is a self - clearing bit 1 reinitializes the cgms/wss readback registers reserved 0 gs_pdc_vps_utc_clear 0 does not reinitialize the gs/pdc/vps/ utc readback registers this is a self - clearing bit 1 refreshes the gs/pdc/vps/utc readback registers reserved 0 vitc_clear 0 does not reinitialize the vitc readback registers this is a self - clearing bit 1 reinitializes the vitc readback registers reserved 0 0x79 vdp_cca p_data_0 (read o nly) ccap_byte_1[7:0] x x x x x x x x decoded byte 1 of ccap 0x7a vdp_ccap_data_1 (read o nly) ccap_byte_2[7:0] x x x x x x x x decoded byte 2 of ccap 0x7d vdp_cgms_wss_data_0 (read o nly) cgms_crc[5:2] x x x x decoded crc sequence for cgms reserved 0 0 0 0 0x7e vdp_cgms_wss_data_1 (read o nly) cgms_wss[13:8] x x x x x x decoded cgms/wss data cgms_crc[1:0] x x decoded crc sequence for cgms 0x7f vdp_cgms_wss_data_2 (read o nly) cgms_wss[7:0] x x x x x x x x deco ded cgms/wss data 0x84 vdp_gs_vps_pdc_utc_0 (read o nly) gs_vps_pdc_utc_byte_0[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x85 vdp_gs_vps_pdc_utc_1 (read o nly) gs_vps_pdc_utc_byte_1[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data
data sheet adv7180 rev. g | page 105 of 120 user sub map bit (shading indicates default state) address register bit description 7 6 5 4 3 2 1 0 comments notes 0x86 vdp_gs_vps_pdc_utc_2 (read o nly) gs_vps_pdc_utc_byte_2[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x87 vdp_gs_vps_pdc_utc_3 (read o nly) gs_vps_pdc_utc_byte_3[7:0] x x x x x x x x decoded gemstar/vps/pdc/utc data 0x88 vdp_vps_pdc_utc_4 (read o nly) vps_pdc_utc_byte_4[7:0] x x x x x x x x decoded vps/pdc/utc data 0x89 vdp_vps_pdc_utc_5 (read o nly) vps_pdc_utc_byte_5[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8a vdp_vps_pdc_utc_6 (read o nly) vps_pdc_utc_byte_6[7:0] x x x x x x x x decod ed vps/pdc/utc data 0x8b vdp_vps_pdc_utc_7 (read o nly) vps_pdc_utc_byte_7[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8c vdp_vps_pdc_utc_8 (read o nly) vps_pdc_utc_byte_8[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8d vdp_vps_pdc_utc_9 (read o nly) vps_pdc_utc_byte_9[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8e vdp_vps_pdc_utc_10 (read o nly) vps_pdc_utc_byte_10[7:0] x x x x x x x x decoded vps/pdc/utc data 0x8f vdp_vps_pdc_utc_11 ( r ead o nly) vps_pdc_utc_byte_11[7:0] x x x x x x x x dec oded vps/pdc/utc data 0x90 vdp_vps_pdc_utc_12 (read o nly) vps_pdc_utc_byte_12[7:0] x x x x x x x x decoded vps/pdc/utc data 0x92 vdp_vitc_data_0 (read o nly) vitc_data_0[7:0] x x x x x x x x decoded vitc data 0x93 vdp_vitc_data_1 (read o nly) vitc_data _1[7:0] x x x x x x x x decoded vitc data 0x94 vdp_vitc_data_2 (read o nly) vitc_data_2[7:0] x x x x x x x x decoded vitc data 0x95 vdp_vitc_data_3 (r ead only) vitc_data_3[7:0] x x x x x x x x decoded vitc data 0x96 vdp_vitc_data_4 (read o nly) vitc_da ta_4[7:0] x x x x x x x x decoded vitc data 0x97 vdp_vitc_data_5 (read o nly) vitc_data_5[7:0] x x x x x x x x decoded vitc data 0x98 vdp_vitc_data_6 (read o nly) vitc_data_6[7:0] x x x x x x x x decoded vitc data 0x99 vdp_vitc_data_7 (read o nly) vitc_ data_7[7:0] x x x x x x x x decoded vitc data 0x9a vdp_vitc_data_8 (read o nly) vitc_data_8[7:0] x x x x x x x x decoded vitc data 0x9b vdp_vitc_calc_crc (read o nly) vitc_crc[7:0] x x x x x x x x decoded vitc crc data 0x9c vdp_output_sel reserved 0 0 0 0 wss_cgms_cb_change 0 disable content - based updating of cgms and wss data the available bit shows the availability of data only when its content has changed 1 enable content - based updating of cgms and wss data gs_vps_p dc_utc_cb_change 0 disable content - based updating of gemstar, vps, pdc, and utc data 1 enable content - based updating of gemstar, vps, pdc, and utc data i 2 c_gs_vps_pdc_utc[1:0] 0 0 gemstar_1/gemstar_2 standard expected to b e decoded 0 1 vps 1 0 pdc 1 1 utc 1 x indicates a bit that keeps the last written value. 2 shading indicates default v alues.
adv7180 data sheet rev. g | page 106 of 120 i 2 c programming exampl es 64- lead lqfp mode 1 cvbs input (composite video on a in 2) all standards are supported through autodetect, 8 - bit, 4:2:2 itu - r bt.656 output on p15 to p8 for the 64 -lead lqfp . table 109 . mode 1 cvbs input register address (hex) register value (hex) notes 00 01 insel = cvbs in on a in 2 04 57 enable sfl 17 41 select sh1 31 02 clear newav_mode, sav/eav to suit adv video encoders 3d a2 mwe en able manual window, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimization 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 2 s - video input (y on a in 3 and c on a in 6) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p15 to p8 for the 64 - lead lqfp . table 110 . mode 2 s - video input register address (hex) register value (hex) notes 00 08 insel = y/c, y = a in 3, c = a in 6 04 57 enable sfl 31 02 clear newavmode, sav/eav t o suit adv video encoders 3d a2 mwe enable manual window, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimization 58 04 mandatory write; this must be performed for correct operation 0e 80 hidden space 55 81 adc configuration 0e 00 us er space mode 3 525i/625i yprpb input (y on a in 1, pr on a in 4, and pb on a in 5) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p15 to p8 for the 64 - lead lqfp . table 111 . mode 3 yprpb input register ad dress (hex) register value (hex) notes 00 09 insel = yprpb, y = a in 1, pr = a in 4, pb = a in 5 31 02 clear newav_mode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window 3e 6a blm optimization 3f a0 adi recommended 0e 80 hidden space 55 81 adc configuration 0e 00 user space
data sheet adv7180 rev. g | page 107 of 120 48- lead lqfp mode 1 cvbs input (composite video on a in 2) all standards are supported through autodetect, 8 - bit, 4:2:2 itu - r bt.656 output on p0 to p7 for the 32- lead lqfp. table 112 . mode 1 cvbs input register address (hex) register value (hex) notes 00 01 insel = cvbs in on a in 2 04 57 enable sfl 17 41 select sh1 31 02 clear newav_mode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window, color kill threshold to 2 3e 6a b lm optimization 3f a0 bgb optimization 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 2 s - video input (y on a in 3 and c on a in 6) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p0 to p7 for the 32- lead l q f p. table 113 . mode 2 s - video input register address (hex) register value (hex) notes 00 08 insel = y/c, y = a in 3, c = a in 6 04 57 enable sfl 31 02 clear newavmode, sav/eav to suit adv video encoders 3d a2 mwe enable manual wind ow, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimization 58 04 mandatory write; this must be performed for correct operation 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 3 525i/625i yprpb input (y on a in 1, pr on a in 4, and pb on a in 5) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p0 to p7 for the 32- lead lqfp. table 114 . mode 3 yprpb input register address (hex) register value (hex) notes 00 09 insel = yp rpb, y = a in 1, pr = a in 4, pb = a in 5 31 02 clear newav_mode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window 3e 6a blm optimization 3f a0 adi recommended 54 4e adi recommended 0e 80 hidden space 55 81 adc configuration 0e 00 user s pace
adv7180 data sheet rev. g | page 108 of 120 40- lead lfcsp mode 1 cvbs input (composite video on a in 1) all standards are supported through autodetect, 8 - bit, 4:2:2, itu - r bt.656 output on p0 to p7. table 115 . mode 1 cvbs input register address (hex) register value (he x) notes 00 00 insel = cvbs in on a in 1 04 57 enable sfl 17 41 select sh1 31 02 clear newavmode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimization 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 2 s - video input (y on a in 1 and c on a in 2) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p0 to p7. table 116 . mode 2 s - video input register addre ss (hex) register value (hex) notes 00 06 insel = y/c, y = a in 1, c = a in 2 04 57 enable sfl 31 02 clear newavmode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimizati on 58 04 mandatory write; this must be performed for correct operation 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 3 525i/625i yprpb input (y on a in 1, pb on a in 2, and pr on a in 3) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p0 to p7. table 117 . mode 3 yprpb input register address (hex) register value (hex) notes 00 09 insel = yprpb, y = a in 1, pb = a in 2, pr = a in 3 31 02 clear newavmode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window 3e 6a blm optimization 3f a0 adi recommended 0e 80 hidden space 55 81 adc configuration 0e 00 user space
data sheet adv7180 rev. g | page 109 of 120 32- lead lfcsp mode 1 cvbs input (composite video on a in 1) all standards are supported through autodetect, 8 - bi t, 4:2:2, itu - r bt.656 output on p0 to p7. table 118 . mode 1 cvbs input register address (hex) register value (hex) notes 00 00 insel = cvbs in on a in 1 04 57 enable sfl 17 41 select sh1 31 02 clear newavmode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimization 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 2 s - video input (y on a in 1 and c on a in 2) all standards are sup ported through autodetect, 8 - bit, itu - r bt.656 output on p0 to p7. table 119 . mode 2 s - video input register address (hex) register value (hex) notes 00 06 insel = y/c, y = a in 1, c = a in 2 04 57 enable sfl 31 02 clear newavmode, sa v/eav to suit adv video encoders 3d a2 mwe enable manual window, color kill threshold to 2 3e 6a blm optimization 3f a0 bgb optimization 58 04 mandatory write; this must be performed for correct operation 0e 80 hidden space 55 81 adc configuration 0e 00 user space mode 3 525i/625i yprpb input (y on a in 1, pb on a in 2, and pr on a in 3) all standards are supported through autodetect, 8 - bit, itu - r bt.656 output on p0 to p7. table 120 . mode 3 yprpb input register address (hex) reg ister value (hex) notes 00 09 insel = yprpb, y = a in 1, pb = a in 2, pr = a in 3 31 02 clear newavmode, sav/eav to suit adv video encoders 3d a2 mwe enable manual window 3e 6a blm optimization 3f a0 adi recommended 54 4e adi recommended 0e 80 hidden spac e 55 81 adc configuration 0e 00 user space
adv7180 data sheet rev. g | page 110 of 120 pcb layout recommendations the adv7180 is a high precision, high speed, mixed-signal device. to achieve the maximum performance from the part, it is important to have a well laid out pcb. the following is a guide for designing a board using the adv7180. analog interface inputs care should be taken when routing the inputs on the pcb. track lengths should be kept to a minimum, and 75 trace impedances should be used when possible. in addition, trace impedances other than 75 increa se the chance of reflections. power supply decoupling it is recommended to decouple each power supply pin with 0.1 f and 10 nf capacitors. the fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin. in addition, avoid placing the capacitor on the opposite side of the pcb from the adv7180 because doing so interposes inductive vias in the path. the decoupling capacitors should be located between the power plane and the power pin. current should flow from the power plane to the capacitor and then to the power pin. do not apply the power connection between the capacitor and the power pin. placing a via underneath the 100 nf capacitor pads, down to the power plane, is the best approach (see figure 54). 05700-046 supply ground 10nf 100nf via to supply via to gnd figure 54. recommended power supply decoupling it is particularly important to maintain low noise and good stability of p vdd . careful attention must be paid to regulation, filtering, and decoupling. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (a vdd , d vdd , d vddio , and p vdd ). some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least p vdd , from a different, cleaner power source, for example, from a 12 v supply. using a single ground plane for the entire board is also recom- mended. experience has repeatedly shown that the noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. pll place the pll loop filter components as close as possible to the elpf pin. it should also be placed on the same side of the pcb as the adv7180. do not place any digital or other high frequency traces near these components. use the values suggested in this data sheet with tolerances of 10% or less. vrefn and vrefp the circuit associated with these pins should be placed as close as possible and on the same side of the pcb as the adv7180. digital outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance, requiring more current and, in turn, causing more internal digital noise. shorter traces reduce the possibility of reflections. adding a 30 to 50 series resistor can suppress reflections, reduce emi, and reduce the current spikes inside the adv7180. if series resistors are used, place them as close as possible to the adv7180 pins. however, try not to add vias or extra length to the output trace to place the resistors closer. if possible, limit the capacitance that each of the digital outputs drives to less than 15 pf. this can easily be accomplished by keeping traces short and by connecting the outputs to only one device. loading the outputs with excessive capacitance increases the current transients inside the adv7180, creating more digital noise on its power supplies. the 40-lead and 32-lead lfcsp ha ve an exposed metal paddle on the bottom of the package. this paddle must be soldered to pcb ground for proper heat dissipation and for noise and mechanical strength benefits. digital inputs the digital inputs on the adv7180 are designed to work with 1.8 v to 3.3 v signals and are not tolerant of 5 v signals. extra components are needed if 5 v logic signals are required to be applied to the decoder.
data sheet adv7180 rev. g | page 111 of 120 typical circuit connection examples of how to connect the 40-lead lfcsp, 64-lead lqfp, 48-le ad lqfp, and 32-lead lfcsp video decoders are shown in figure 55, figure 56, figure 57, and figure 58. for a detailed schematic of the adv7180 evaluation boards, contact a local analog devices field applications engineer or analog devices distributor. pwrdwn 18 power_down sclk 34 sclk sdata 33 sda a in 1 23 a in 1 a in 2 29 a in 2 a in 3 30 a in 3 reset 31 reset llc 11 llc intrq 38 intrq sfl 2 sfl vs/field 37 vs/field hs 39 hs elpf 19 82nf 10nf p vdd _1.8v 1.69k ? keep close to the adv7180 and on the same side of pcb as the adv7180. external loop filter p0 17 p0 p1 16 p1 p2 10 p2 p3 9p3 p4 8p4 p5 7p5 p6 6p6 p7 5p7 ycrcb 8-bit 656 data p[0:7] vrefn 26 vrefp 25 keep vrefn and vrefp capacitor as close as possible to the adv7180 and on the same side of the pcb as the adv7180. 1m ? 28.63636mhz 47pf 47pf locate close to, and on the same side as, the adv7180. xtal 13 xtal1 12 alsb 32 d vddio 4k? alsb tied hi i 2 c address = 42h alsb tied low i 2 c address = 40h dgnd 40 dgnd 3 dgnd 15 dgnd 35 agnd 28 agnd 21 agnd 24 test_0 22 pvdd 20 dvddio 1 dvddio 4 dvdd 36 dvdd 14 d vddio _3.3v d vdd _1.8v avdd 27 a vdd _1.8v p vdd _1.8v 0.1f 10nf a vdd _1.8 v 0.1f 10nf d vddio 0.1f 10nf d vdd _1.8 v 0.1f 10nf 0.1f 10nf 39? 36 ? 0.1f analog_input_2 a in 2 39? 36 ? 0.1f analog_input_1 a in 1 39? 36 ? 0.1f analog_input_3 a in 3 05700-048 adv7180bcpz lfcsp?40 0.1f figure 55. 40-lead lfcsp typical connection diagram
adv7180 data sheet rev. g | page 112 of 120 0.1f 0 5700-049 sclk 54 sclk sdata 53 sda a in 1 35 a in 1 a in 2 36 a in 2 a in 3 46 a in 3 a in 4 47 a in 4 a in 5 48 a in 5 a in 6 49 a in 6 llc 20 llc 33? 33? elpf 30 82nf 10nf p vdd _1.8v 1.69k ? keep close to the adv7180 and on the same side of pcb as the adv7180. external loop filter p0 26 p0 p1 25 p1 p2 19 p2 p3 18 p3 p4 17 p4 p5 16 p5 p6 15 p6 p7 14 p7 p[0:7] p8 8p8 p9 7p9 p10 6p10 p11 5p11 p12 62 p12 p13 61 p13 p14 60 p14 p15 59 p15 p[8:15] vrefn 39 vrefp 38 1m ? 28.63636mhz 47pf 47pf xtal 22 xtal1 21 alsb 52 d vddio _3.3v 4k ? agnd 32 agnd 37 agnd 43 test_0 34 dgnd 3 dgnd 10 dgnd 24 dgnd 57 dvdd 58 avdd 40 pvdd 31 dvddio 4 dvddio 11 dvdd 23 p vdd _1.8v 0.1f 10nf d vdd _1.8v d vdd _1.8v 0.1f 10nf a vdd _1.8v 0.1f 10nf d vddio _3.3v 10nf 0.1f 10nf 0.1f d vddio _3.3v 10nf 0.1f 39? 36 ? 0.1f a nalog_input_4 cr a in 4 39? 36 ? 0.1f a nalog_input_3 yc_y a in 3 39? 36 ? 0.1f a nalog_input_2 cvbs a in 2 39? 36 ? 0.1f a nalog_input_1 y a in 1 39? 36 ? 0.1f a nalog_input_5 cb a in 5 39? 36 ? 0.1f a nalog_input_6 yc_c a in 6 reset 51 reset intrq 1 int gpo3 55 gpo3 gpo2 56 gpo2 gpo1 12 gpo1 gpo0 13 gpo0 vs 64 vsync field 63 field hs 2 hs sfl 9 nc 27, 28, 33, 41, 42, 44, 45, 50 sfl pwrdwn 29 power_down nc = no connect adv7180bstz lqfp?64 the suggested input arrangement is as seen on the eval board and is directly supported by insel. tie hi: i 2 c address = 42 tie low: i 2 c address = 40 data bus p[0:7] p[8:15] 8-bit output mode n/a 656/601 ycbcr 16-bit output mode cbcr y keep vrefn and vrefp capacitor as close as possible to the adv7180 and on the same side of the pcb as the adv7180. figure 56. 64-lead lqfp typical connection diagram
data sheet adv7180 rev. g | page 113 of 120 0.1f 05700-061 sclk 40 sclk sdata 39 sda a in 1 26 a in 1 a in 2 27 a in 2 a in 3 33 a in 3 a in 4 34 a in 4 a in 5 35 a in 5 a in 6 36 a in 6 llc 14 llc 33? 33? elpf 24 82nf 10nf p vdd _1.8v 1.69k ? keep close to the adv7180 and on the same side of pcb as the adv7180. external loop filter p0 22 p0 p1 20 p1 p2 12 p2 p3 11 p3 p4 10 p4 p5 9p5 p6 8p6 p7 7p7 p[0:7] vrefn 30 vrefp 29 1m ? 28.63636mhz 47pf 47pf xtal 17 xtal1 16 alsb 38 d vddio _3.3v 4k? agnd 23 agnd 28 agnd 32 dgnd 1 dgnd 13 dgnd 19 dgnd 43 dvdd 18 avdd 31 pvdd 25 dvddio 4 dvddio 2 dvdd 44 p vdd _1.8v 0.1f 10nf d vdd _1.8v d vdd _1.8v 0.1f 10nf a vdd _1.8v 0.1f 10nf d vddio _3.3v 10nf 0.1f 10nf 0.1f d vddio _3.3v 10nf 0.1f 39 ? 36 ? 0.1f analog_input_4 cr a in 4 39 ? 36 ? 0.1f analog_input_3 yc_y a in 3 39 ? 36 ? 0.1f analog_input_2 cvbs a in 2 39 ? 36 ? 0.1f analog_input_1 y a in 1 39 ? 36 ? 0.1f analog_input_5 cb a in 5 39 ? 36 ? 0.1f analog_input_6 yc_c a in 6 reset 37 reset intrq 46 int gpo3 41 gpo3 gpo2 42 gpo2 gpo1 6 gpo1 gpo0 5 gpo0 vs/field 45 vs/field hs 47 hs sfl 3 nc 15, 48 sfl pwrdwn 21 power_down adv7180wbst48z lqfp?48 the suggested input arrangement is as seen on the eval board and is directly supported by insel. tie hi: i 2 c address = 42 tie low: i 2 c address = 40 notes 1. nc = no connect. * refer to analog devices crystal application note for proper capacitor loading * keep vrefn and vrefp capacitor as close as possible to the adv7180 and on the same side of the pcb as the adv7180. figure 57. 48-lead lqfp typical connection diagram
adv7180 data sheet rev. g | page 114 of 120 0.1f sclk 28 sclk sdata 27 sda 19 23 24 reset 25 reset llc 11 llc intrq 32 intrq sfl 4 sfl vs/field 31 vs/field hs 1 hs elpf 17 82nf 10nf 1.69k ? keep close to the adv7180 and on the same side of pcb as the adv7180. external loop filter p0 16 p0 p1 15 p1 p2 10 p2 p3 9p3 p4 8p4 p5 7p5 p6 6p6 p7 5p7 p[0:7] vrefn 21 vrefp 20 28.63636mhz 47pf 47pf locate close to, and on the same side as, the adv7180. xtal 13 xtal1 12 alsb 26 4k? dgnd 2 dgnd 29 pvdd 18 dvddio 3 dvdd 14 dvdd 30 avdd 22 0.1f 10nf 0.1f 10nf 0.1f 10nf 0.1f 10nf 39 ? 36 ? 0.1f analog_input_2 39 ? 36 ? 0.1f analog_input_1 39 ? 36 ? 0.1f analog_input_3 05700-056 adv7180kcp32z lfcsp?32 keep vrefn and vrefp capacitor as close as possible to the adv7180 and on the same side of the pcb as the adv7180. a in 1 a in 1 a in 2 a in 2 a in 3 a in 3 a in 1 a in 2 a in 3 d vdd _1.8 v d vddio a vdd _1.8 v d vddio _3.3v d vdd _1.8v a vdd _1.8v p vdd _1.8v ycrcb 8-bit 656 data d vddio alsb tied hi i 2 c addr ess = 42h alsb tied low i 2 c addr ess = 40h p vdd _1.8v 1m ? figure 58. 32-lead lfcsp typical connection diagram
data sheet adv7180 rev. g | page 115 of 120 outline dimensions 08-16-2010-b 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad pin 1 indicator seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220-whhd-5 with exception to exposed pad dimension. figure 59 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very t hin quad (cp - 32 - 12) dimensions shown in millimeters 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indic at or 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref sea ting plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarit y 0.08 0.80 max 0.65 ty p 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indic at or 0.60 max 0.60 max 0.25 min exposed p ad (bot t om view) compliant t o jedec s t andards mo-220-vjjd-2 072108- a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 60 . 40 - lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp - 40 -1) dimensions shown in millimeters
adv7180 data sheet rev. g | page 116 of 120 compliant t o jedec s t andards ms-026-bcd 051706- a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 61 . 64 - lead low profile quad flat package [lqfp] 10 mm 10 mm body (st - 64 - 2) dimensions shown in millimeters compliant t o jedec s t andards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706- a figure 62 . 4 8- lead low profile quad flat package [lqfp] 7 mm 7 mm body (st- 48) dimensions shown in millimeters
data sheet adv7180 rev. g | page 117 of 120 ordering guide model 1 , 2 temperature range package description package option adv7180 k cp32z ?1 0c to + 70c 32- lead lead frame chip scale package [lfcsp_wq] cp -32 -12 adv7180 k cp32z -rl ?1 0c to + 70c 32- lead lead frame chip scale package [lfcsp_wq] cp -32 -12 adv7180bcpz ?40c to +85c 40- lead lead frame chip scale package [lfcsp_vq] cp -40 -1 adv718 0bcpz - reel ?40c to +85c 40- lead lead frame chip scale package [lfcsp_vq] cp -40 -1 adv7180bstz ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 adv7180bstz - reel ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 adv71 80wbcp32z ?40c to +85c 32- lead lead frame chip scale package [lfcsp_w q] cp -32 -12 adv7180wbcp32z -rl ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32 -12 adv7180wbcpz ?40c to +125c 40- lead lead fram e chip scale package [lfcsp_vq] cp- 40 -1 adv7180wbcpz - reel ?40c to +125c 40- lead lead frame chip scale package [lfcsp_vq] cp -40 -1 adv7180wbstz ?40c to +125c 64- lead low profile quad flat package [lqfp] st- 64 -2 adv7180wbstz - reel ?40c to +125c 64- lead low profile quad flat package [lqfp] st- 64 -2 adv7180wbst48z ?40c to +85c 48 - lead low profile quad flat package [lqfp] st - 48 adv7180wbst48z - rl ?40c to +85c 48- lead low profile quad flat package [lqfp] st- 48 adv7180kst48z ?10c to +70c 48- lead low profile quad flat package [lqfp] st- 48 adv7180kst48z -rl ?10c to +70c 48- lead low profile quad flat package [lqfp] st- 48 adv7180bst48z ?40c to +85c 48- lead low profile quad flat package [lqfp] st- 48 adv7180bst48z -rl ?40c to +85c 48- lead low profile quad flat package [lqfp] st- 48 adv7180bcp32z ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-12 adv7180bcp32z -rl ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-12 eval - adv7180lqebz evaluation board for the 64 - lead lqfp eval - adv7180lfebz evaluation board for the 40 - lead lfcsp eval - adv7180- 32ebz evaluation board for the 32 - lead lfcsp eval - adv7180- 48ebz evaluation board for the 48 - lead lqfp 1 z = rohs compliant part. 2 w = qualified for automotive applications. automotive products the adv7180w models are available with controlled manufacturing to sup port the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models, and designers should review the product spe cifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information a nd to obtain t he specific automotive reliability reports for these models. note that the adv7180 is a pb - free, environmentally friendly product. it is manufactured using the most up - to - date materials and processes. the coating on the leads of each device is 100% pure sn electroplate. the device is suitable for pb - free applications and can withstand surface - mount soldering at up to 255c (5c). in addition, it is backward - compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be soldered with sn/pb solder pastes at conventional reflow temperatures of 220c to 235c.
adv7180 data sheet rev. g | page 118 of 120 notes
data sheet adv7180 rev. g | page 119 of 120 notes
adv7180 data sheet rev. g | page 120 of 120 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semi conductors) . ? 2006 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05700 -0- 3 /12(g)

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